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pl.dtsi
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/*
* CAUTION: This file is automatically generated by Xilinx.
* Version: XSCT 2022.1
* Today is: Wed Aug 28 12:58:45 2024
*/
/dts-v1/;
/plugin/;
/ {
fragment@0 {
target = <&fpga_full>;
overlay0: __overlay__ {
#address-cells = <2>;
#size-cells = <2>;
firmware-name = "design_1_wrapper.bit.bin";
resets = <&zynqmp_reset 116>;
};
};
fragment@1 {
target = <&amba>;
overlay1: __overlay__ {
afi0: afi0 {
compatible = "xlnx,afi-fpga";
config-afi = < 0 0>, <1 0>, <2 0>, <3 0>, <4 0>, <5 0>, <6 0>, <7 0>, <8 0>, <9 0>, <10 0>, <11 0>, <12 0>, <13 0>, <14 0xa00>, <15 0x200>;
};
clocking0: clocking0 {
#clock-cells = <0>;
assigned-clock-rates = <124998749>;
assigned-clocks = <&zynqmp_clk 71>;
clock-output-names = "fabric_clk";
clocks = <&zynqmp_clk 71>;
compatible = "xlnx,fclk";
};
clocking1: clocking1 {
#clock-cells = <0>;
assigned-clock-rates = <124998749>;
assigned-clocks = <&zynqmp_clk 72>;
clock-output-names = "fabric_clk";
clocks = <&zynqmp_clk 72>;
compatible = "xlnx,fclk";
};
};
};
fragment@2 {
target = <&amba>;
overlay2: __overlay__ {
#address-cells = <2>;
#size-cells = <2>;
axi_iic: i2c@a0000000 {
#address-cells = <1>;
#size-cells = <0>;
clock-names = "s_axi_aclk";
clocks = <&misc_clk_0>;
compatible = "xlnx,axi-iic-2.1", "xlnx,xps-iic-2.00.a";
interrupt-names = "iic2intc_irpt";
interrupt-parent = <&axi_intc>;
interrupts = <0 2>;
reg = <0x0 0xa0000000 0x0 0x10000>;
};
misc_clk_0: misc_clk_0 {
#clock-cells = <0>;
clock-frequency = <124998749>;
compatible = "fixed-clock";
};
axi_intc: interrupt-controller@a0010000 {
#interrupt-cells = <2>;
clock-names = "s_axi_aclk";
clocks = <&misc_clk_0>;
compatible = "xlnx,axi-intc-4.1", "xlnx,xps-intc-1.00.a";
interrupt-controller ;
reg = <0x0 0xa0010000 0x0 0x10000>;
xlnx,kind-of-intr = <0x0>;
xlnx,num-intr-inputs = <0xc>;
};
camif_ias1_mipi_rx_to_video: mipi_rx_to_video@a0020000 {
/* This is a place holder node for a custom IP, user may need to update the entries */
clock-names = "dphy_clk_p", "dphy_clk_n", "s00_axi_aclk";
clocks = <&misc_clk_1>, <&misc_clk_1>, <&misc_clk_0>;
compatible = "xlnx,mipi-rx-to-video-1.0";
interrupt-names = "irq";
interrupt-parent = <&axi_intc>;
interrupts = <8 2>;
reg = <0x0 0xa0020000 0x0 0x10000>;
xlnx,s00-axi-addr-width = <0x7>;
xlnx,s00-axi-data-width = <0x20>;
};
misc_clk_1: misc_clk_1 {
#clock-cells = <0>;
clock-frequency = <100000000>;
compatible = "fixed-clock";
};
camif_ias1_v_frm_wr: v_frmbuf_wr@b0000000 {
#dma-cells = <1>;
clock-names = "ap_clk";
clocks = <&misc_clk_2>;
compatible = "xlnx,v-frmbuf-wr-2.4", "xlnx,axi-frmbuf-wr-v2.2";
interrupt-names = "interrupt";
interrupt-parent = <&axi_intc>;
interrupts = <9 2>;
reg = <0x0 0xb0000000 0x0 0x10000>;
reset-gpios = <&gpio_slice_axi_gpio 4 1>;
xlnx,dma-addr-width = <32>;
xlnx,dma-align = <32>;
xlnx,max-height = <3120>;
xlnx,max-width = <4208>;
xlnx,pixels-per-clock = <4>;
xlnx,s-axi-ctrl-addr-width = <0x7>;
xlnx,s-axi-ctrl-data-width = <0x20>;
xlnx,vid-formats = "y8", "y10";
xlnx,video-width = <10>;
};
misc_clk_2: misc_clk_2 {
#clock-cells = <0>;
clock-frequency = <249997498>;
compatible = "fixed-clock";
};
camif_rpi_mipi_rx_to_video: mipi_rx_to_video@a0030000 {
/* This is a place holder node for a custom IP, user may need to update the entries */
clock-names = "dphy_clk_p", "dphy_clk_n", "s00_axi_aclk";
clocks = <&misc_clk_1>, <&misc_clk_1>, <&misc_clk_0>;
compatible = "xlnx,mipi-rx-to-video-1.0";
interrupt-names = "irq";
interrupt-parent = <&axi_intc>;
interrupts = <10 2>;
reg = <0x0 0xa0030000 0x0 0x10000>;
xlnx,s00-axi-addr-width = <0x7>;
xlnx,s00-axi-data-width = <0x20>;
};
camif_rpi_v_frm_wr: v_frmbuf_wr@b0010000 {
#dma-cells = <1>;
clock-names = "ap_clk";
clocks = <&misc_clk_2>;
compatible = "xlnx,v-frmbuf-wr-2.4", "xlnx,axi-frmbuf-wr-v2.2";
interrupt-names = "interrupt";
interrupt-parent = <&axi_intc>;
interrupts = <11 2>;
reg = <0x0 0xb0010000 0x0 0x10000>;
reset-gpios = <&gpio_slice_axi_gpio 5 1>;
xlnx,dma-addr-width = <32>;
xlnx,dma-align = <16>;
xlnx,max-height = <2160>;
xlnx,max-width = <3840>;
xlnx,pixels-per-clock = <2>;
xlnx,s-axi-ctrl-addr-width = <0x7>;
xlnx,s-axi-ctrl-data-width = <0x20>;
xlnx,vid-formats = "y8", "y10";
xlnx,video-width = <10>;
};
clk_wiz: clk_wiz@80000000 {
#clock-cells = <1>;
clock-names = "s_axi_aclk", "clk_in1";
clock-output-names = "0x80000000-clk_ctrl", "0x80000000-clk_mm", "0x80000000-clk_vcu", "0x80000000-clk_scale";
clocks = <&misc_clk_0>, <&zynqmp_clk 71>;
compatible = "xlnx,clk-wiz-6.0", "xlnx,clocking-wizard";
reg = <0x0 0x80000000 0x0 0x10000>;
speed-grade = <2>;
};
gpio_slice_axi_gpio: gpio@a0040000 {
#gpio-cells = <2>;
clock-names = "s_axi_aclk";
clocks = <&misc_clk_0>;
compatible = "xlnx,axi-gpio-2.0", "xlnx,xps-gpio-1.00.a";
gpio-controller ;
reg = <0x0 0xa0040000 0x0 0x10000>;
xlnx,all-inputs = <0x0>;
xlnx,all-inputs-2 = <0x0>;
xlnx,all-outputs = <0x1>;
xlnx,all-outputs-2 = <0x0>;
xlnx,dout-default = <0x00000000>;
xlnx,dout-default-2 = <0x00000000>;
xlnx,gpio-width = <0x10>;
xlnx,gpio2-width = <0x20>;
xlnx,interrupt-present = <0x0>;
xlnx,is-dual = <0x0>;
xlnx,tri-default = <0xFFFFFFFF>;
xlnx,tri-default-2 = <0xFFFFFFFF>;
};
isp_pipe_isp: xil_isp_lite@a0050000 {
/* This is a place holder node for a custom IP, user may need to update the entries */
clock-names = "pclk", "s00_axi_aclk";
clocks = <&misc_clk_0>, <&misc_clk_0>;
compatible = "xlnx,xil-isp-lite-1.0";
interrupt-names = "irq";
interrupt-parent = <&axi_intc>;
interrupts = <3 2>;
reg = <0x0 0xa0050000 0x0 0x10000>;
xlnx,s00-axi-addr-width = <0x10>;
xlnx,s00-axi-data-width = <0x20>;
};
isp_pipe_v_frm_rd: v_frmbuf_rd@b0020000 {
#dma-cells = <1>;
clock-names = "ap_clk";
clocks = <&misc_clk_2>;
compatible = "xlnx,v-frmbuf-rd-2.4", "xlnx,axi-frmbuf-rd-v2.2";
interrupt-names = "interrupt";
interrupt-parent = <&axi_intc>;
interrupts = <2 2>;
reg = <0x0 0xb0020000 0x0 0x10000>;
reset-gpios = <&gpio_slice_axi_gpio 1 1>;
xlnx,dma-addr-width = <32>;
xlnx,dma-align = <8>;
xlnx,max-height = <2160>;
xlnx,max-width = <3840>;
xlnx,pixels-per-clock = <1>;
xlnx,s-axi-ctrl-addr-width = <0x7>;
xlnx,s-axi-ctrl-data-width = <0x20>;
xlnx,vid-formats = "y8", "y10";
xlnx,video-width = <10>;
};
isp_pipe_v_frm_wr_1: v_frmbuf_wr@b0030000 {
#dma-cells = <1>;
clock-names = "ap_clk";
clocks = <&misc_clk_2>;
compatible = "xlnx,v-frmbuf-wr-2.4", "xlnx,axi-frmbuf-wr-v2.2";
interrupt-names = "interrupt";
interrupt-parent = <&axi_intc>;
interrupts = <5 2>;
reg = <0x0 0xb0030000 0x0 0x10000>;
reset-gpios = <&gpio_slice_axi_gpio 2 1>;
xlnx,dma-addr-width = <32>;
xlnx,dma-align = <8>;
xlnx,max-height = <2160>;
xlnx,max-width = <3840>;
xlnx,pixels-per-clock = <1>;
xlnx,s-axi-ctrl-addr-width = <0x7>;
xlnx,s-axi-ctrl-data-width = <0x20>;
xlnx,vid-formats = "rgb888", "bgr888", "uyvy", "yuyv", "nv12";
xlnx,video-width = <8>;
};
isp_pipe_v_frm_wr_2: v_frmbuf_wr@b0040000 {
#dma-cells = <1>;
clock-names = "ap_clk";
clocks = <&misc_clk_2>;
compatible = "xlnx,v-frmbuf-wr-2.4", "xlnx,axi-frmbuf-wr-v2.2";
interrupt-names = "interrupt";
interrupt-parent = <&axi_intc>;
interrupts = <7 2>;
reg = <0x0 0xb0040000 0x0 0x10000>;
reset-gpios = <&gpio_slice_axi_gpio 3 1>;
xlnx,dma-addr-width = <32>;
xlnx,dma-align = <8>;
xlnx,max-height = <2160>;
xlnx,max-width = <3840>;
xlnx,pixels-per-clock = <1>;
xlnx,s-axi-ctrl-addr-width = <0x7>;
xlnx,s-axi-ctrl-data-width = <0x20>;
xlnx,vid-formats = "rgb888", "bgr888", "uyvy", "yuyv", "nv12";
xlnx,video-width = <8>;
};
isp_pipe_vip_1: xil_vip@a0060000 {
/* This is a place holder node for a custom IP, user may need to update the entries */
clock-names = "pclk", "pclk_scale", "s00_axi_aclk";
clocks = <&misc_clk_0>, <&misc_clk_0>, <&misc_clk_0>;
compatible = "xlnx,xil-vip-1.0";
interrupt-names = "irq";
interrupt-parent = <&axi_intc>;
interrupts = <4 2>;
reg = <0x0 0xa0060000 0x0 0x10000>;
xlnx,s00-axi-addr-width = <0x10>;
xlnx,s00-axi-data-width = <0x20>;
};
isp_pipe_vip_2: xil_vip@a0070000 {
/* This is a place holder node for a custom IP, user may need to update the entries */
clock-names = "pclk", "pclk_scale", "s00_axi_aclk";
clocks = <&misc_clk_0>, <&misc_clk_0>, <&misc_clk_0>;
compatible = "xlnx,xil-vip-1.0";
interrupt-names = "irq";
interrupt-parent = <&axi_intc>;
interrupts = <6 2>;
reg = <0x0 0xa0070000 0x0 0x10000>;
xlnx,s00-axi-addr-width = <0x10>;
xlnx,s00-axi-data-width = <0x20>;
};
vcu: vcu@a0100000 {
#address-cells = <2>;
#clock-cells = <1>;
#size-cells = <2>;
clock-names = "pll_ref", "aclk", "vcu_core_enc", "vcu_mcu_enc", "vcu_core_dec", "vcu_mcu_dec";
clocks = <&misc_clk_3>, <&misc_clk_0>, <&vcu 0>, <&vcu 1>, <&vcu 2>, <&vcu 3>;
compatible = "xlnx,vcu-1.2", "xlnx,vcu";
interrupt-names = "vcu_host_interrupt";
interrupt-parent = <&axi_intc>;
interrupts = <1 2>;
ranges ;
reg = <0x0 0xa0140000 0x0 0x1000>, <0x0 0xa0141000 0x0 0x1000>;
reg-names = "vcu_slcr", "logicore";
reset-gpios = <&gpio_slice_axi_gpio 0 0 1>;
encoder: al5e@a0100000 {
compatible = "al,al5e-1.2", "al,al5e";
interrupt-parent = <&axi_intc>;
interrupts = <1 2>;
reg = <0x0 0xa0100000 0x0 0x10000>;
};
decoder: al5d@a0120000 {
compatible = "al,al5d-1.2", "al,al5d";
interrupt-parent = <&axi_intc>;
interrupts = <1 2>;
reg = <0x0 0xa0120000 0x0 0x10000>;
};
};
misc_clk_3: misc_clk_3 {
#clock-cells = <0>;
clock-frequency = <33332999>;
compatible = "fixed-clock";
};
};
};
};