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stm32: Add initial support for H5 MCUs.
This commit adds initial support for STM32H5xx MCUs. The following features have been confirmed to be working on an STM32H573: - UART over REPL and USB CDC - USB CDC and MSC - internal flash filesystem - machine.Pin - machine.SPI transfers with DMA - machine.ADC - machine.RTC - pyb.LED - pyb.Switch - pyb.rng - mboot Signed-off-by: Damien George <[email protected]>
1 parent bd7196e commit 61339aa

33 files changed

+624
-115
lines changed

‎ports/stm32/Makefile

+8-2
Original file line numberDiff line numberDiff line change
@@ -403,7 +403,7 @@ HAL_SRC_C += $(addprefix $(STM32LIB_HAL_BASE)/Src/stm32$(MCU_SERIES)xx_,\
403403
ll_utils.c \
404404
)
405405

406-
ifeq ($(MCU_SERIES),$(filter $(MCU_SERIES),f4 f7 g0 g4 h7 l0 l4 wb))
406+
ifeq ($(MCU_SERIES),$(filter $(MCU_SERIES),f4 f7 g0 g4 h5 h7 l0 l4 wb))
407407
HAL_SRC_C += $(addprefix $(STM32LIB_HAL_BASE)/Src/stm32$(MCU_SERIES)xx_,\
408408
hal_pcd.c \
409409
hal_pcd_ex.c \
@@ -432,12 +432,18 @@ $(BUILD)/$(STM32LIB_HAL_BASE)/Src/stm32$(MCU_SERIES)xx_hal_mmc.o: CFLAGS += -Wno
432432
endif
433433
endif
434434

435-
ifeq ($(MCU_SERIES),$(filter $(MCU_SERIES),f4 f7 g0 g4 h7))
435+
ifeq ($(MCU_SERIES),$(filter $(MCU_SERIES),f4 f7 g0 g4 h5 h7))
436436
HAL_SRC_C += $(addprefix $(STM32LIB_HAL_BASE)/Src/stm32$(MCU_SERIES)xx_,\
437437
hal_dma_ex.c \
438438
)
439439
endif
440440

441+
ifeq ($(MCU_SERIES),$(filter $(MCU_SERIES),h5))
442+
HAL_SRC_C += $(addprefix $(STM32LIB_HAL_BASE)/Src/stm32$(MCU_SERIES)xx_,\
443+
hal_icache.c \
444+
)
445+
endif
446+
441447
ifeq ($(MCU_SERIES),$(filter $(MCU_SERIES),f0 f4 f7))
442448
HAL_SRC_C += $(addprefix $(STM32LIB_HAL_BASE)/Src/stm32$(MCU_SERIES)xx_, hal_can.c)
443449
else ifeq ($(MCU_SERIES),$(filter $(MCU_SERIES),g0 g4 h7))

‎ports/stm32/adc.c

+15-7
Original file line numberDiff line numberDiff line change
@@ -102,7 +102,7 @@
102102
#define ADC_CAL2 ((uint16_t *)(ADC_CAL_ADDRESS + 4))
103103
#define ADC_CAL_BITS (12)
104104

105-
#elif defined(STM32G0) || defined(STM32G4)
105+
#elif defined(STM32G0) || defined(STM32G4) || defined(STM32H5)
106106

107107
#define ADC_SCALE_V (((float)VREFINT_CAL_VREF) / 1000.0f)
108108
#define ADC_CAL_ADDRESS VREFINT_CAL_ADDR
@@ -160,6 +160,8 @@
160160
#define VBAT_DIV (4)
161161
#elif defined(STM32G0) || defined(STM32G4)
162162
#define VBAT_DIV (3)
163+
#elif defined(STM32H5)
164+
#define VBAT_DIV (4)
163165
#elif defined(STM32H723xx) || defined(STM32H733xx) || \
164166
defined(STM32H743xx) || defined(STM32H747xx) || \
165167
defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || \
@@ -248,6 +250,10 @@ STATIC bool is_adcx_channel(int channel) {
248250
handle.Instance = ADCx;
249251
return __HAL_ADC_IS_CHANNEL_INTERNAL(channel)
250252
|| IS_ADC_CHANNEL(&handle, __HAL_ADC_DECIMAL_NB_TO_CHANNEL(channel));
253+
#elif defined(STM32H5)
254+
// The first argument to the IS_ADC_CHANNEL macro is unused.
255+
return __HAL_ADC_IS_CHANNEL_INTERNAL(channel)
256+
|| IS_ADC_CHANNEL(NULL, __HAL_ADC_DECIMAL_NB_TO_CHANNEL(channel));
251257
#else
252258
#error Unsupported processor
253259
#endif
@@ -257,7 +263,7 @@ STATIC void adc_wait_for_eoc_or_timeout(ADC_HandleTypeDef *adcHandle, int32_t ti
257263
uint32_t tickstart = HAL_GetTick();
258264
#if defined(STM32F4) || defined(STM32F7) || defined(STM32L1)
259265
while ((adcHandle->Instance->SR & ADC_FLAG_EOC) != ADC_FLAG_EOC) {
260-
#elif defined(STM32F0) || defined(STM32G0) || defined(STM32G4) || defined(STM32H7) || defined(STM32L4) || defined(STM32WB)
266+
#elif defined(STM32F0) || defined(STM32G0) || defined(STM32G4) || defined(STM32H5) || defined(STM32H7) || defined(STM32L4) || defined(STM32WB)
261267
while (READ_BIT(adcHandle->Instance->ISR, ADC_FLAG_EOC) != ADC_FLAG_EOC) {
262268
#else
263269
#error Unsupported processor
@@ -278,6 +284,8 @@ STATIC void adcx_clock_enable(ADC_HandleTypeDef *adch) {
278284
__HAL_RCC_ADC_CLK_ENABLE();
279285
#elif defined(STM32G4)
280286
__HAL_RCC_ADC12_CLK_ENABLE();
287+
#elif defined(STM32H5)
288+
__HAL_RCC_ADC_CLK_ENABLE();
281289
#elif defined(STM32H7)
282290
if (adch->Instance == ADC3) {
283291
__HAL_RCC_ADC3_CLK_ENABLE();
@@ -335,7 +343,7 @@ STATIC void adcx_init_periph(ADC_HandleTypeDef *adch, uint32_t resolution) {
335343
adch->Init.LowPowerAutoWait = DISABLE;
336344
adch->Init.DataAlign = ADC_DATAALIGN_RIGHT;
337345
adch->Init.DMAContinuousRequests = DISABLE;
338-
#elif defined(STM32G0) || defined(STM32G4) || defined(STM32L4) || defined(STM32WB)
346+
#elif defined(STM32G0) || defined(STM32G4) || defined(STM32H5) || defined(STM32L4) || defined(STM32WB)
339347
adch->Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
340348
adch->Init.ScanConvMode = ADC_SCAN_DISABLE;
341349
adch->Init.LowPowerAutoWait = DISABLE;
@@ -354,7 +362,7 @@ STATIC void adcx_init_periph(ADC_HandleTypeDef *adch, uint32_t resolution) {
354362
#endif
355363
#if defined(STM32G0)
356364
HAL_ADCEx_Calibration_Start(adch);
357-
#elif defined(STM32G4) || defined(STM32L4) || defined(STM32WB)
365+
#elif defined(STM32G4) || defined(STM32H5) || defined(STM32L4) || defined(STM32WB)
358366
HAL_ADCEx_Calibration_Start(adch, ADC_SINGLE_ENDED);
359367
#endif
360368
}
@@ -415,7 +423,7 @@ STATIC void adc_config_channel(ADC_HandleTypeDef *adc_handle, uint32_t channel)
415423
} else {
416424
sConfig.SamplingTime = ADC_SAMPLETIME_12CYCLES_5;
417425
}
418-
#elif defined(STM32G4) || defined(STM32L4) || defined(STM32WB)
426+
#elif defined(STM32G4) || defined(STM32H5) || defined(STM32L4) || defined(STM32WB)
419427
if (__HAL_ADC_IS_CHANNEL_INTERNAL(channel)) {
420428
sConfig.SamplingTime = ADC_SAMPLETIME_247CYCLES_5;
421429
} else {
@@ -599,7 +607,7 @@ STATIC mp_obj_t adc_read_timed(mp_obj_t self_in, mp_obj_t buf_in, mp_obj_t freq_
599607
// for subsequent samples we can just set the "start sample" bit
600608
#if defined(STM32F4) || defined(STM32F7) || defined(STM32L1)
601609
self->handle.Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
602-
#elif defined(STM32F0) || defined(STM32G0) || defined(STM32G4) || defined(STM32H7) || defined(STM32L4) || defined(STM32WB)
610+
#elif defined(STM32F0) || defined(STM32G0) || defined(STM32G4) || defined(STM32H5) || defined(STM32H7) || defined(STM32L4) || defined(STM32WB)
603611
SET_BIT(self->handle.Instance->CR, ADC_CR_ADSTART);
604612
#else
605613
#error Unsupported processor
@@ -709,7 +717,7 @@ STATIC mp_obj_t adc_read_timed_multi(mp_obj_t adc_array_in, mp_obj_t buf_array_i
709717
// ADC is started: set the "start sample" bit
710718
#if defined(STM32F4) || defined(STM32F7) || defined(STM32L1)
711719
adc->handle.Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
712-
#elif defined(STM32F0) || defined(STM32G0) || defined(STM32G4) || defined(STM32H7) || defined(STM32L4) || defined(STM32WB)
720+
#elif defined(STM32F0) || defined(STM32G0) || defined(STM32G4) || defined(STM32H5) || defined(STM32H7) || defined(STM32L4) || defined(STM32WB)
713721
SET_BIT(adc->handle.Instance->CR, ADC_CR_ADSTART);
714722
#else
715723
#error Unsupported processor

‎ports/stm32/adc.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -48,7 +48,7 @@ static inline void adc_deselect_vbat(ADC_TypeDef *adc, uint32_t channel) {
4848
adc_common = ADC_COMMON_REGISTER(0);
4949
#elif defined(STM32F7)
5050
adc_common = ADC123_COMMON;
51-
#elif defined(STM32G4)
51+
#elif defined(STM32G4) || defined(STM32H5)
5252
adc_common = ADC12_COMMON;
5353
#elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xx) || defined(STM32H7B3xxQ)
5454
adc_common = ADC12_COMMON;

‎ports/stm32/dac.c

+4-4
Original file line numberDiff line numberDiff line change
@@ -66,7 +66,7 @@
6666

6767
#if defined(MICROPY_HW_ENABLE_DAC) && MICROPY_HW_ENABLE_DAC
6868

69-
#if defined(STM32H7)
69+
#if defined(STM32H5) || defined(STM32H7)
7070
#define DAC DAC1
7171
#endif
7272

@@ -124,7 +124,7 @@ STATIC uint32_t TIMx_Config(mp_obj_t timer) {
124124

125125
STATIC void dac_deinit(uint32_t dac_channel) {
126126
DAC->CR &= ~(DAC_CR_EN1 << dac_channel);
127-
#if defined(STM32G0) || defined(STM32G4) || defined(STM32H7) || defined(STM32L4)
127+
#if defined(STM32G0) || defined(STM32G4) || defined(STM32H5) || defined(STM32H7) || defined(STM32L4)
128128
DAC->MCR = (DAC->MCR & ~(DAC_MCR_MODE1_Msk << dac_channel)) | (DAC_OUTPUTBUFFER_DISABLE << dac_channel);
129129
#else
130130
DAC->CR |= DAC_CR_BOFF1 << dac_channel;
@@ -142,7 +142,7 @@ STATIC void dac_config_channel(uint32_t dac_channel, uint32_t trig, uint32_t out
142142
DAC->CR &= ~(DAC_CR_EN1 << dac_channel);
143143
uint32_t cr_off = DAC_CR_DMAEN1 | DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1;
144144
uint32_t cr_on = trig;
145-
#if defined(STM32G0) || defined(STM32G4) || defined(STM32H7) || defined(STM32L4)
145+
#if defined(STM32G0) || defined(STM32G4) || defined(STM32H5) || defined(STM32H7) || defined(STM32L4)
146146
DAC->MCR = (DAC->MCR & ~(DAC_MCR_MODE1_Msk << dac_channel)) | (outbuf << dac_channel);
147147
#else
148148
cr_off |= DAC_CR_BOFF1;
@@ -259,7 +259,7 @@ STATIC mp_obj_t pyb_dac_init_helper(pyb_dac_obj_t *self, size_t n_args, const mp
259259
__DAC_CLK_ENABLE();
260260
#elif defined(STM32H7)
261261
__HAL_RCC_DAC12_CLK_ENABLE();
262-
#elif defined(STM32F0) || defined(STM32G0) || defined(STM32G4) || defined(STM32L4)
262+
#elif defined(STM32F0) || defined(STM32G0) || defined(STM32G4) || defined(STM32H5) || defined(STM32L4)
263263
__HAL_RCC_DAC1_CLK_ENABLE();
264264
#elif defined(STM32L1)
265265
__HAL_RCC_DAC_CLK_ENABLE();

‎ports/stm32/dma.c

+107-8
Original file line numberDiff line numberDiff line change
@@ -80,7 +80,7 @@ typedef union {
8080
struct _dma_descr_t {
8181
#if defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
8282
DMA_Stream_TypeDef *instance;
83-
#elif defined(STM32F0) || defined(STM32G0) || defined(STM32G4) || defined(STM32L0) || defined(STM32L1) || defined(STM32L4) || defined(STM32WB) || defined(STM32WL)
83+
#elif defined(STM32F0) || defined(STM32G0) || defined(STM32G4) || defined(STM32H5) || defined(STM32L0) || defined(STM32L1) || defined(STM32L4) || defined(STM32WB) || defined(STM32WL)
8484
DMA_Channel_TypeDef *instance;
8585
#else
8686
#error "Unsupported Processor"
@@ -92,6 +92,23 @@ struct _dma_descr_t {
9292

9393
// Default parameters to dma_init() shared by spi and i2c; Channel and Direction
9494
// vary depending on the peripheral instance so they get passed separately
95+
#if defined(STM32H5)
96+
static const DMA_InitTypeDef dma_init_struct_spi_i2c = {
97+
.Request = 0, // set by dma_init_handle
98+
.BlkHWRequest = DMA_BREQ_SINGLE_BURST,
99+
.Direction = 0, // set by dma_init_handle
100+
.SrcInc = 0, // set by dma_init_handle
101+
.DestInc = 0, // set by dma_init_handle
102+
.SrcDataWidth = DMA_SRC_DATAWIDTH_BYTE,
103+
.DestDataWidth = DMA_DEST_DATAWIDTH_BYTE,
104+
.Priority = DMA_LOW_PRIORITY_LOW_WEIGHT,
105+
.SrcBurstLength = 1,
106+
.DestBurstLength = 1,
107+
.TransferAllocatedPort = DMA_SRC_ALLOCATED_PORT0 | DMA_DEST_ALLOCATED_PORT0,
108+
.TransferEventMode = DMA_TCEM_BLOCK_TRANSFER,
109+
.Mode = DMA_NORMAL, // DMA_NORMAL or DMA_PFCTRL (peripheral flow control mode)
110+
};
111+
#else
95112
static const DMA_InitTypeDef dma_init_struct_spi_i2c = {
96113
#if defined(STM32F4) || defined(STM32F7)
97114
.Channel = 0,
@@ -112,6 +129,7 @@ static const DMA_InitTypeDef dma_init_struct_spi_i2c = {
112129
.PeriphBurst = DMA_PBURST_INC4
113130
#endif
114131
};
132+
#endif
115133

116134
#if MICROPY_HW_ENABLE_I2S
117135
// Default parameters to dma_init() for i2s; Channel and Direction
@@ -678,6 +696,39 @@ static const uint8_t dma_irqn[NSTREAM] = {
678696
#endif
679697
};
680698

699+
#elif defined(STM32H5)
700+
701+
#define NCONTROLLERS (2)
702+
#define NSTREAMS_PER_CONTROLLER (8)
703+
#define NSTREAM (NCONTROLLERS * NSTREAMS_PER_CONTROLLER)
704+
705+
#define DMA_SUB_INSTANCE_AS_UINT8(dma_channel) (dma_channel)
706+
707+
#define DMA1_ENABLE_MASK (0x00ff) // Bits in dma_enable_mask corresponding to GPDMA1
708+
#define DMA2_ENABLE_MASK (0xff00) // Bits in dma_enable_mask corresponding to GPDMA2
709+
710+
const dma_descr_t dma_SPI_2_RX = { GPDMA1_Channel0, GPDMA1_REQUEST_SPI2_RX, dma_id_0, &dma_init_struct_spi_i2c };
711+
const dma_descr_t dma_SPI_2_TX = { GPDMA1_Channel1, GPDMA1_REQUEST_SPI2_TX, dma_id_1, &dma_init_struct_spi_i2c };
712+
713+
static const uint8_t dma_irqn[NSTREAM] = {
714+
GPDMA1_Channel0_IRQn,
715+
GPDMA1_Channel1_IRQn,
716+
GPDMA1_Channel2_IRQn,
717+
GPDMA1_Channel3_IRQn,
718+
GPDMA1_Channel4_IRQn,
719+
GPDMA1_Channel5_IRQn,
720+
GPDMA1_Channel6_IRQn,
721+
GPDMA1_Channel7_IRQn,
722+
GPDMA2_Channel0_IRQn,
723+
GPDMA2_Channel1_IRQn,
724+
GPDMA2_Channel2_IRQn,
725+
GPDMA2_Channel3_IRQn,
726+
GPDMA2_Channel4_IRQn,
727+
GPDMA2_Channel5_IRQn,
728+
GPDMA2_Channel6_IRQn,
729+
GPDMA2_Channel7_IRQn,
730+
};
731+
681732
#elif defined(STM32H7)
682733

683734
#define NCONTROLLERS (2)
@@ -761,6 +812,13 @@ volatile dma_idle_count_t dma_idle;
761812
#if defined(DMA2)
762813
#define DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & RCC_AHBENR_DMA2EN) != 0)
763814
#endif
815+
#elif defined(STM32H5)
816+
#define DMA1_IS_CLK_ENABLED() (__HAL_RCC_GPDMA1_IS_CLK_ENABLED())
817+
#define DMA2_IS_CLK_ENABLED() (__HAL_RCC_GPDMA2_IS_CLK_ENABLED())
818+
#define __HAL_RCC_DMA1_CLK_ENABLE __HAL_RCC_GPDMA1_CLK_ENABLE
819+
#define __HAL_RCC_DMA2_CLK_ENABLE __HAL_RCC_GPDMA2_CLK_ENABLE
820+
#define __HAL_RCC_DMA1_CLK_DISABLE __HAL_RCC_GPDMA1_CLK_DISABLE
821+
#define __HAL_RCC_DMA2_CLK_DISABLE __HAL_RCC_GPDMA2_CLK_DISABLE
764822
#else
765823
#define DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN) != 0)
766824
#define DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN) != 0)
@@ -1093,6 +1151,34 @@ void DMA2_Channel8_IRQHandler(void) {
10931151
}
10941152
#endif
10951153

1154+
#elif defined(STM32H5)
1155+
1156+
#define DEFINE_IRQ_HANDLER(periph, channel, id) \
1157+
void GPDMA##periph##_Channel##channel##_IRQHandler(void) { \
1158+
IRQ_ENTER(GPDMA##periph##_Channel##channel##_IRQn); \
1159+
if (dma_handle[id] != NULL) { \
1160+
HAL_DMA_IRQHandler(dma_handle[id]); \
1161+
} \
1162+
IRQ_EXIT(GPDMA##periph##_Channel##channel##_IRQn); \
1163+
}
1164+
1165+
DEFINE_IRQ_HANDLER(1, 0, dma_id_0)
1166+
DEFINE_IRQ_HANDLER(1, 1, dma_id_1)
1167+
DEFINE_IRQ_HANDLER(1, 2, dma_id_2)
1168+
DEFINE_IRQ_HANDLER(1, 3, dma_id_3)
1169+
DEFINE_IRQ_HANDLER(1, 4, dma_id_4)
1170+
DEFINE_IRQ_HANDLER(1, 5, dma_id_5)
1171+
DEFINE_IRQ_HANDLER(1, 6, dma_id_6)
1172+
DEFINE_IRQ_HANDLER(1, 7, dma_id_7)
1173+
DEFINE_IRQ_HANDLER(2, 0, dma_id_8)
1174+
DEFINE_IRQ_HANDLER(2, 1, dma_id_9)
1175+
DEFINE_IRQ_HANDLER(2, 2, dma_id_10)
1176+
DEFINE_IRQ_HANDLER(2, 3, dma_id_11)
1177+
DEFINE_IRQ_HANDLER(2, 4, dma_id_12)
1178+
DEFINE_IRQ_HANDLER(2, 5, dma_id_13)
1179+
DEFINE_IRQ_HANDLER(2, 6, dma_id_14)
1180+
DEFINE_IRQ_HANDLER(2, 7, dma_id_15)
1181+
10961182
#elif defined(STM32L0)
10971183

10981184
void DMA1_Channel1_IRQHandler(void) {
@@ -1276,7 +1362,7 @@ static void dma_enable_clock(dma_id_t dma_id) {
12761362
}
12771363
}
12781364
}
1279-
#if defined(DMA2)
1365+
#if defined(DMA2) || defined(GPDMA2)
12801366
else {
12811367
if (((old_enable_mask & DMA2_ENABLE_MASK) == 0) && !DMA2_IS_CLK_ENABLED()) {
12821368
__HAL_RCC_DMA2_CLK_ENABLE();
@@ -1310,13 +1396,25 @@ void dma_init_handle(DMA_HandleTypeDef *dma, const dma_descr_t *dma_descr, uint3
13101396
dma->Instance = dma_descr->instance;
13111397
dma->Init = *dma_descr->init;
13121398
dma->Init.Direction = dir;
1313-
#if defined(STM32G0) || defined(STM32G4) || defined(STM32H7) || defined(STM32L0) || defined(STM32L4) || defined(STM32WB) || defined(STM32WL)
1399+
#if defined(STM32G0) || defined(STM32G4) || defined(STM32H5) || defined(STM32H7) || defined(STM32L0) || defined(STM32L4) || defined(STM32WB) || defined(STM32WL)
13141400
dma->Init.Request = dma_descr->sub_instance;
13151401
#else
13161402
#if !defined(STM32F0) && !defined(STM32L1)
13171403
dma->Init.Channel = dma_descr->sub_instance;
13181404
#endif
13191405
#endif
1406+
1407+
#if defined(STM32H5)
1408+
// Configure src/dest settings based on the DMA direction.
1409+
if (dir == DMA_MEMORY_TO_PERIPH) {
1410+
dma->Init.SrcInc = DMA_SINC_INCREMENTED;
1411+
dma->Init.DestInc = DMA_DINC_FIXED;
1412+
} else if (dir == DMA_PERIPH_TO_MEMORY) {
1413+
dma->Init.SrcInc = DMA_SINC_FIXED;
1414+
dma->Init.DestInc = DMA_DINC_INCREMENTED;
1415+
}
1416+
#endif
1417+
13201418
// half of __HAL_LINKDMA(data, xxx, *dma)
13211419
// caller must implement other half by doing: data->xxx = dma
13221420
dma->Parent = data;
@@ -1337,11 +1435,12 @@ void dma_init(DMA_HandleTypeDef *dma, const dma_descr_t *dma_descr, uint32_t dir
13371435

13381436
dma_enable_clock(dma_id);
13391437

1340-
#if defined(STM32G0) || defined(STM32G4) || defined(STM32H7) || defined(STM32L0) || defined(STM32L1) || defined(STM32L4) || defined(STM32WB) || defined(STM32WL)
1438+
#if defined(STM32G0) || defined(STM32G4) || defined(STM32H5) || defined(STM32H7) || defined(STM32L0) || defined(STM32L1) || defined(STM32L4) || defined(STM32WB) || defined(STM32WL)
13411439
// Always reset and configure the H7 and G0/G4/H7/L0/L4/WB/WL DMA peripheral
13421440
// (dma->State is set to HAL_DMA_STATE_RESET by memset above)
13431441
// TODO: understand how L0/L4 DMA works so this is not needed
13441442
HAL_DMA_DeInit(dma);
1443+
dma->Parent = data; // HAL_DMA_DeInit may clear Parent, so set it again
13451444
HAL_DMA_Init(dma);
13461445
NVIC_SetPriority(IRQn_NONNEG(dma_irqn[dma_id]), IRQ_PRI_DMA);
13471446
#else
@@ -1418,7 +1517,7 @@ static void dma_idle_handler(uint32_t tick) {
14181517

14191518
static const uint32_t controller_mask[] = {
14201519
DMA1_ENABLE_MASK,
1421-
#if defined(DMA2)
1520+
#if defined(DMA2) || defined(GPDMA2)
14221521
DMA2_ENABLE_MASK,
14231522
#endif
14241523
};
@@ -1435,15 +1534,15 @@ static void dma_idle_handler(uint32_t tick) {
14351534
if (controller == 0) {
14361535
__HAL_RCC_DMA1_CLK_DISABLE();
14371536
#if defined(STM32G4)
1438-
#if defined(DMA2)
1537+
#if defined(DMA2) || defined(GPDMA2)
14391538
if (__HAL_RCC_DMA2_IS_CLK_DISABLED())
14401539
#endif
14411540
{
14421541
__HAL_RCC_DMAMUX1_CLK_DISABLE();
14431542
}
14441543
#endif
14451544
}
1446-
#if defined(DMA2)
1545+
#if defined(DMA2) || defined(GPDMA2)
14471546
else {
14481547
__HAL_RCC_DMA2_CLK_DISABLE();
14491548
#if defined(STM32G4)
@@ -1514,7 +1613,7 @@ void dma_nohal_start(const dma_descr_t *descr, uint32_t src_addr, uint32_t dst_a
15141613
dma->CCR |= DMA_CCR_EN;
15151614
}
15161615

1517-
#elif defined(STM32G0) || defined(STM32WB) || defined(STM32WL)
1616+
#elif defined(STM32G0) || defined(STM32H5) || defined(STM32WB) || defined(STM32WL)
15181617

15191618
// These functions are currently not implemented or needed for this MCU.
15201619

‎ports/stm32/dma.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,7 @@
2828

2929
typedef struct _dma_descr_t dma_descr_t;
3030

31-
#if defined(STM32F0) || defined(STM32F4) || defined(STM32F7) || defined(STM32G0) || defined(STM32H7)
31+
#if defined(STM32F0) || defined(STM32F4) || defined(STM32F7) || defined(STM32G0) || defined(STM32H5) || defined(STM32H7)
3232

3333
extern const dma_descr_t dma_I2C_1_RX;
3434
extern const dma_descr_t dma_SPI_3_RX;

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