VHDL Gen submodule

GSimas · GSimas · commit 1887f264452a · 2017-09-22T22:26:36.000-03:00
diff --git a/.gitmodules b/.gitmodules
@@ -1,3 +1,6 @@
 [submodule "Examples/DeepLearning"]
 	path = Examples/DeepLearning
 	url = https://github.com/paulobatista-phd/deep-learning
+[submodule "Examples/VhdlGen"]
+	path = Examples/VhdlGen
+	url = https://github.com/andrecp/vhdl_gen
diff --git a/Examples/VhdlGen b/Examples/VhdlGen
@@ -0,0 +1 @@
+Subproject commit 97b20ab9c286eb561f8e77d9c1d5d65d37152ef0
