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Merge branch 'feat/ci' into 'master'
meta: add CI configuration Closes atsams-rs#21 See merge request embedded-rust/atsamx7x-hal!14
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‎.ci/Dockerfile

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FROM rust:1.61.0-slim
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RUN apt-get update && apt-get install -y \
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binutils-arm-none-eabi \
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git \
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&& rm -rf /var/lib/apt/lists/*
7+
8+
RUN rustup target add thumbv7em-none-eabihf && \
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rustup component add rustfmt && \
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rustup component add clippy

‎.ci/README.md

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This directory contains the `Dockerfile` used in the CI of the HAL. See [GitLab Container Registry documentation](https://git.grepit.se/embedded-rust/atsamx7x-hal/container_registry) for update instructions.

‎.gitlab-ci.yml

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image: "registry.git.grepit.se/embedded-rust/atsamx7x-hal"
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stages:
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- HAL
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- examples
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- lint
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default:
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before_script:
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- rustup show
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samv71q21b:
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stage: HAL
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script:
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- cd hal
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- cargo check --features samv71q21b,unproven
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same70n21b:
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stage: HAL
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script:
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- cd hal
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- cargo check --features same70n21b,unproven
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e70:
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stage: examples
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script:
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- cd boards/atsame70_xpro
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- cargo check --examples
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v71:
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stage: examples
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script:
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- cd boards/atsamv71_xult
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- cargo check --examples
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fmt:
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stage: lint
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needs: []
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script:
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- cd hal
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- cargo fmt -- --check
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- cd ../boards/atsame70_xpro
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- cargo fmt -- --check
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- cd ../atsamv71_xult
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- cargo fmt -- --check
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clippy:
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stage: lint
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allow_failure: true
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needs: ["samv71q21b"]
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script:
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- cd hal
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- cargo clippy --no-deps --features samv71q21b,unproven
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- cd ../boards/atsame70_xpro
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- cargo clippy --examples --no-deps
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- cd ../atsamv71_xult
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- cargo clippy --examples --no-deps

‎hal/build.rs

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@@ -6,7 +6,7 @@ fn main() -> Result<(), &'static str> {
66
fn feat(f: &str) -> bool {
77
env::var(format!(
88
"CARGO_FEATURE_{}",
9-
f.to_ascii_uppercase().replace("-", "_")
9+
f.to_ascii_uppercase().replace('-', "_")
1010
))
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.is_ok()
1212
}

‎hal/src/efc.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@ use crate::target_device::EFC;
66
/// The voltage which drives the MCU.
77
///
88
/// Refer to §58 and §59.
9-
#[derive(PartialEq)]
9+
#[derive(Eq, PartialEq)]
1010
pub enum VddioLevel {
1111
/// VDDIO = 3.3V, typical
1212
V3,
@@ -49,7 +49,7 @@ impl Efc {
4949
/// The number of flash wait states for a read operation.
5050
///
5151
/// Note: The number of cycles a read takes is 1 + FWS.
52-
#[derive(Debug, PartialEq, Copy, Clone)]
52+
#[derive(Debug, Eq, PartialEq, Copy, Clone)]
5353
#[repr(u8)]
5454
enum FlashWaitStates {
5555
Zero,

‎hal/src/pio/bank.rs

Lines changed: 36 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -97,18 +97,18 @@ impl<B: PinBank> Iterator for BankInterruptsIter<B> {
9797
match self.idx {
9898
32.. => {
9999
// We have iterated over all pins: nothing more to do.
100-
return None;
100+
None
101101
}
102102
idx if self.irq & (1 << idx) != 0 => {
103103
// Pin number `idx` had a pending interrupt.
104104
let pin = self.idx;
105-
self.idx = self.idx + 1;
105+
self.idx += 1;
106106
Some(pin)
107107
}
108108
_ => {
109109
// Pin number `idx` did not have a pending interrupt:
110110
// advance to the next pin.
111-
self.idx = self.idx + 1;
111+
self.idx += 1;
112112
self.next()
113113
}
114114
}
@@ -253,28 +253,41 @@ macro_rules! bank {
253253
macro_rules! banks {
254254
(
255255
$(
256+
$( #[$cfg1:meta] )?
256257
$Bank:ident {
257258
$(
258-
$( #[$cfg:meta] )?
259+
$( #[$cfg2:meta] )?
259260
($Id:ident, $NUM:literal),
260261
)+
261262
}
262263
)+
263264
) => {
264265
$(
265-
$(
266-
$( #[$cfg] )?
267-
pin_id!($Bank, $Id, $NUM);
268-
)+
269-
bank!(
270-
$Bank,
271-
$(
272-
$( #[$cfg] )?
273-
$Id,
274-
)+
275-
);
276-
impl PinBank for $Bank {
277-
const DYN: DynBank = DynBank::$Bank;
266+
paste! {
267+
$( #[$cfg1] )?
268+
mod [<$Bank:lower _impl>] {
269+
use super::*;
270+
271+
$(
272+
$( #[$cfg2] )?
273+
pin_id!($Bank, $Id, $NUM);
274+
)+
275+
276+
bank!(
277+
$Bank,
278+
$(
279+
$( #[$cfg2] )?
280+
$Id,
281+
)+
282+
);
283+
284+
impl PinBank for $Bank {
285+
const DYN: DynBank = DynBank::$Bank;
286+
}
287+
288+
}
289+
$( #[$cfg1] )?
290+
pub use [<$Bank:lower _impl>]::*;
278291
}
279292
)+
280293
};
@@ -288,6 +301,7 @@ banks!(
288301
(PA3, 3),
289302
(PA4, 4),
290303
(PA5, 5),
304+
#[cfg(feature = "pins-144")]
291305
(PA6, 6),
292306
(PA7, 7),
293307
(PA8, 8),
@@ -311,6 +325,7 @@ banks!(
311325
(PA26, 26),
312326
(PA27, 27),
313327
(PA28, 28),
328+
#[cfg(feature = "pins-144")]
314329
(PA29, 29),
315330
(PA30, 30),
316331
(PA31, 31),
@@ -331,6 +346,7 @@ banks!(
331346
(PB13, 13),
332347
}
333348

349+
#[cfg(feature = "pins-144")]
334350
C {
335351
(PC0, 0),
336352
(PC1, 1),
@@ -390,17 +406,20 @@ banks!(
390406
(PD20, 20),
391407
(PD21, 21),
392408
(PD22, 22),
409+
#[cfg(feature = "pins-144")]
393410
(PD23, 23),
394411
(PD24, 24),
395412
(PD25, 25),
396413
(PD26, 26),
397414
(PD27, 27),
398415
(PD28, 28),
416+
#[cfg(feature = "pins-144")]
399417
(PD29, 29),
400418
(PD30, 30),
401419
(PD31, 31),
402420
}
403421

422+
#[cfg(feature = "pins-144")]
404423
E {
405424
(PE0, 0),
406425
(PE1, 1),

‎hal/src/pio/dynpin.rs

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -82,12 +82,14 @@ pub enum DynPinMode {
8282

8383
/// Value-level `enum` regresenting [`Pin`] banks
8484
#[doc(hidden)]
85-
#[derive(PartialEq, Clone, Copy)]
85+
#[derive(Eq, PartialEq, Clone, Copy)]
8686
pub enum DynBank {
8787
A,
8888
B,
89+
#[cfg(feature = "pins-144")]
8990
C,
9091
D,
92+
#[cfg(feature = "pins-144")]
9193
E,
9294
}
9395

@@ -96,16 +98,18 @@ impl DynBank {
9698
match self {
9799
Self::A => PIOA::ptr(),
98100
Self::B => PIOB::ptr(),
101+
#[cfg(feature = "pins-144")]
99102
Self::C => PIOC::ptr(),
100103
Self::D => PIOD::ptr(),
104+
#[cfg(feature = "pins-144")]
101105
Self::E => PIOE::ptr(),
102106
}
103107
}
104108
}
105109

106110
/// Value-level `struct` representing [`Pin`] IDs
107111
#[doc(hidden)]
108-
#[derive(PartialEq, Clone, Copy)]
112+
#[derive(Eq, PartialEq, Clone, Copy)]
109113
pub struct DynPinId {
110114
pub bank: DynBank,
111115
pub num: u8,

‎hal/src/pio/mod.rs

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -102,12 +102,13 @@ use crate::target_device::{
102102
// All PIO banks below use the same register block definition.
103103
pioa::RegisterBlock,
104104

105+
// Banks common to all chip sizes.
105106
PIOA,
106107
PIOB,
107-
PIOC,
108108
PIOD,
109-
PIOE,
110109
};
110+
#[cfg(feature = "pins-144")]
111+
use crate::target_device::{PIOC, PIOE};
111112

112113
pub mod pin;
113114
pub use pin::*;

‎hal/src/pio/pin.rs

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@ pub(in crate::pio) struct Registers<I: PinId> {
2020
id: PhantomData<I>,
2121
}
2222

23-
unsafe impl<I: PinId> RegisterInterface for Registers<I> {
23+
impl<I: PinId> RegisterInterface for Registers<I> {
2424
#[inline]
2525
fn id(&self) -> DynPinId {
2626
I::DYN
@@ -226,21 +226,25 @@ where
226226
}
227227

228228
#[inline]
229+
#[allow(clippy::bool_comparison)]
229230
pub(in crate::pio) fn _is_written_high(&self) -> bool {
230231
self.regs.read_out_pin() == true
231232
}
232233

233234
#[inline]
235+
#[allow(clippy::bool_comparison)]
234236
pub(in crate::pio) fn _is_written_low(&self) -> bool {
235237
self.regs.read_out_pin() == false
236238
}
237239

238240
#[inline]
241+
#[allow(clippy::bool_comparison)]
239242
pub(in crate::pio) fn _is_read_high(&self) -> bool {
240243
self.regs.read_in_pin() == true
241244
}
242245

243246
#[inline]
247+
#[allow(clippy::bool_comparison)]
244248
pub(in crate::pio) fn _is_read_low(&self) -> bool {
245249
self.regs.read_in_pin() == false
246250
}

‎hal/src/pio/reg.rs

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@ use crate::target_device::pioa::RegisterBlock;
22

33
use super::dynpin::*;
44

5-
pub(in crate::pio) unsafe trait RegisterInterface {
5+
pub(in crate::pio) trait RegisterInterface {
66
fn id(&self) -> DynPinId;
77

88
/// Return the `u32` mask to set/clear a bit for this
@@ -21,14 +21,14 @@ pub(in crate::pio) unsafe trait RegisterInterface {
2121
fn change_mode(&mut self, mode: DynPinMode) {
2222
match mode {
2323
DynPinMode::Reset => unimplemented!(),
24-
DynPinMode::Peripheral(a) => self.into_peripheral(a),
25-
DynPinMode::Output => self.into_output(),
26-
DynPinMode::Input => self.into_input(),
24+
DynPinMode::Peripheral(a) => self.as_peripheral(a),
25+
DynPinMode::Output => self.as_output(),
26+
DynPinMode::Input => self.as_input(),
2727
}
2828
}
2929

3030
#[inline]
31-
fn into_peripheral(&mut self, cfg: DynPeripheral) {
31+
fn as_peripheral(&mut self, cfg: DynPeripheral) {
3232
use DynPeripheral::*;
3333
let (sr0, sr1) = match cfg {
3434
A => (false, false),
@@ -58,7 +58,7 @@ pub(in crate::pio) unsafe trait RegisterInterface {
5858
}
5959

6060
#[inline]
61-
fn into_output(&mut self) {
61+
fn as_output(&mut self) {
6262
// set initial output state as low (0)
6363
self.write_pin(false);
6464

@@ -75,7 +75,7 @@ pub(in crate::pio) unsafe trait RegisterInterface {
7575
}
7676

7777
#[inline]
78-
fn into_input(&mut self) {
78+
fn as_input(&mut self) {
7979
// take pin from peripheral
8080
self.reg().pio_per.write(|w| unsafe { w.bits(self.mask()) });
8181

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