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[DAG] Avoid a crash when checking size of scalable type in visitANDLike
Fixes llvm#80744. This transform doesn't handled vectors at all, The fixed length ones pass the first check, but would fail the constant operand checks which immediate follow. This patch takes the simplest approach, and just guards the transform for scalar integers.
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2 files changed

+57
-3
lines changed

2 files changed

+57
-3
lines changed

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6376,7 +6376,7 @@ SDValue DAGCombiner::visitANDLike(SDValue N0, SDValue N1, SDNode *N) {
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// TODO: Rewrite this to return a new 'AND' instead of using CombineTo.
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if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
6379-
VT.getSizeInBits() <= 64 && N0->hasOneUse()) {
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VT.isScalarInteger() && VT.getSizeInBits() <= 64 && N0->hasOneUse()) {
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if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
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if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) {
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// Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal

llvm/test/CodeGen/RISCV/and-add-lsr.ll

Lines changed: 56 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+v < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I
4-
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs -mattr=+v < %s \
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; RUN: | FileCheck %s -check-prefix=RV64I
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define i32 @and_add_lsr(i32 %x, i32 %y) {
@@ -23,3 +23,57 @@ define i32 @and_add_lsr(i32 %x, i32 %y) {
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%r = and i32 %2, %1
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ret i32 %r
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}
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; Make sure we don't crash on fixed length vectors
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define <2 x i32> @and_add_lsr_vec(<2 x i32> %x, <2 x i32> %y) {
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; RV32I-LABEL: and_add_lsr_vec:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a0, 1
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; RV32I-NEXT: addi a0, a0, -1
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; RV32I-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
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; RV32I-NEXT: vadd.vx v8, v8, a0
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; RV32I-NEXT: vsrl.vi v9, v9, 20
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; RV32I-NEXT: vand.vv v8, v9, v8
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: and_add_lsr_vec:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a0, 1
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; RV64I-NEXT: addi a0, a0, -1
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; RV64I-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
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; RV64I-NEXT: vadd.vx v8, v8, a0
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; RV64I-NEXT: vsrl.vi v9, v9, 20
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; RV64I-NEXT: vand.vv v8, v9, v8
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; RV64I-NEXT: ret
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%1 = add <2 x i32> %x, splat (i32 4095)
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%2 = lshr <2 x i32> %y, splat (i32 20)
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%r = and <2 x i32> %2, %1
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ret <2 x i32> %r
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}
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; Make sure we don't crash on scalable vectors
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define <vscale x 2 x i32> @and_add_lsr_vec2(<vscale x 2 x i32> %x, <vscale x 2 x i32> %y) {
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; RV32I-LABEL: and_add_lsr_vec2:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a0, 1
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; RV32I-NEXT: addi a0, a0, -1
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; RV32I-NEXT: vsetvli a1, zero, e32, m1, ta, ma
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; RV32I-NEXT: vadd.vx v8, v8, a0
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; RV32I-NEXT: vsrl.vi v9, v9, 20
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; RV32I-NEXT: vand.vv v8, v9, v8
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: and_add_lsr_vec2:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a0, 1
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; RV64I-NEXT: addi a0, a0, -1
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; RV64I-NEXT: vsetvli a1, zero, e32, m1, ta, ma
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; RV64I-NEXT: vadd.vx v8, v8, a0
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; RV64I-NEXT: vsrl.vi v9, v9, 20
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; RV64I-NEXT: vand.vv v8, v9, v8
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; RV64I-NEXT: ret
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%1 = add <vscale x 2 x i32> %x, splat (i32 4095)
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%2 = lshr <vscale x 2 x i32> %y, splat (i32 20)
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%r = and <vscale x 2 x i32> %2, %1
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ret <vscale x 2 x i32> %r
79+
}

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