From f1e1b4e97275929dbd0433ee29808594313972cf Mon Sep 17 00:00:00 2001 From: Leandro Lupori Date: Tue, 10 May 2022 17:01:48 -0300 Subject: [PATCH 01/13] target/ppc: Add GEN_PRIV2 GEN_PRIV can't be used in functions that return a value. Add GEN_PRIV2 for this end. --- target/ppc/translate.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index fa34f81c30215..8e345b65956de 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -1273,6 +1273,12 @@ typedef struct opcode_t { gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \ } while (0) +#define GEN_PRIV2(ret) \ + do { \ + gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ + return (ret); \ + } while (0) + #if defined(CONFIG_USER_ONLY) #define CHK_HV GEN_PRIV #define CHK_SV GEN_PRIV From 7287192bb0104c1fcbcfdb8ded3f5d2023fb1b59 Mon Sep 17 00:00:00 2001 From: Leandro Lupori Date: Tue, 10 May 2022 17:08:14 -0300 Subject: [PATCH 02/13] target/ppc: Move tlbie to decode tree Also decode RIC, PRS and R operands. --- target/ppc/cpu_init.c | 4 +- target/ppc/insn32.decode | 7 ++ target/ppc/translate.c | 42 +---------- target/ppc/translate/storage-ctrl-impl.c.inc | 73 ++++++++++++++++++++ 4 files changed, 84 insertions(+), 42 deletions(-) create mode 100644 target/ppc/translate/storage-ctrl-impl.c.inc diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 527ad40fcb946..246b9587f5beb 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6368,7 +6368,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) PPC_FLOAT_EXT | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_MEM_TLBSYNC | + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD | @@ -6585,7 +6585,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) PPC_FLOAT_EXT | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_MEM_TLBSYNC | + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD | diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 39372fe67333f..fdfd24e8bdd17 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -710,3 +710,10 @@ XVTLSBB 111100 ... -- 00010 ..... 111011011 . - @XX2_bf_xb &XL_s s:uint8_t @XL_s ......-------------- s:1 .......... - &XL_s RFEBB 010011-------------- . 0010010010 - @XL_s + +## TLB Management Instructions + +&X_tlbie rb rs ric prs:bool r:bool +@X_tlbie ...... rs:5 - ric:2 prs:1 r:1 rb:5 .......... . &X_tlbie + +TLBIE 011111 ..... - .. . . ..... 0100110010 - @X_tlbie diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 8e345b65956de..379913e9408e8 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -5419,44 +5419,6 @@ static void gen_tlbiel(DisasContext *ctx) #endif /* defined(CONFIG_USER_ONLY) */ } -/* tlbie */ -static void gen_tlbie(DisasContext *ctx) -{ -#if defined(CONFIG_USER_ONLY) - GEN_PRIV; -#else - bool psr = (ctx->opcode >> 17) & 0x1; - TCGv_i32 t1; - - if (ctx->pr) { - /* tlbie is privileged... */ - GEN_PRIV; - } else if (!ctx->hv) { - if (!ctx->gtse || (!psr && ctx->hr)) { - /* - * ... except when GTSE=0 or when PSR=0 and HR=1, making it - * hypervisor privileged. - */ - GEN_PRIV; - } - } - - if (NARROW_MODE(ctx)) { - TCGv t0 = tcg_temp_new(); - tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); - gen_helper_tlbie(cpu_env, t0); - tcg_temp_free(t0); - } else { - gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); - } - t1 = tcg_temp_new_i32(); - tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); - tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); - tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); - tcg_temp_free_i32(t1); -#endif /* defined(CONFIG_USER_ONLY) */ -} - /* tlbsync */ static void gen_tlbsync(DisasContext *ctx) { @@ -6674,6 +6636,8 @@ static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a) #include "translate/branch-impl.c.inc" +#include "translate/storage-ctrl-impl.c.inc" + /* Handles lfdp */ static void gen_dform39(DisasContext *ctx) { @@ -6913,9 +6877,7 @@ GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), * different ISA versions */ GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE), -GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE), GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300), -GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300), GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), #if defined(TARGET_PPC64) GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI), diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc b/target/ppc/translate/storage-ctrl-impl.c.inc new file mode 100644 index 0000000000000..e623731f69627 --- /dev/null +++ b/target/ppc/translate/storage-ctrl-impl.c.inc @@ -0,0 +1,73 @@ +/* + * Power ISA decode for Storage Control instructions + * + * Copyright (c) 2022 Instituto de Pesquisas Eldorado (eldorado.org.br) + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +/* + * Store Control Instructions + */ + +static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local) +{ +#if defined(CONFIG_USER_ONLY) + GEN_PRIV2(true); +#else + TCGv_i32 t1; + int rb, ric; + bool prs, r; + + rb = a->rb; + ric = a->ric; + prs = a->prs; + r = a->r; + + if (ric || prs || r) { + REQUIRE_INSNS_FLAGS2(ctx, ISA300); + } + + if (ctx->pr) { + /* tlbie is privileged... */ + GEN_PRIV2(true); + } else if (!ctx->hv) { + if (!ctx->gtse || (!prs && ctx->hr)) { + /* + * ... except when GTSE=0 or when PRS=0 and HR=1, making it + * hypervisor privileged. + */ + GEN_PRIV2(true); + } + } + + if (NARROW_MODE(ctx)) { + TCGv t0 = tcg_temp_new(); + tcg_gen_ext32u_tl(t0, cpu_gpr[rb]); + gen_helper_tlbie(cpu_env, t0); + tcg_temp_free(t0); + } else { + gen_helper_tlbie(cpu_env, cpu_gpr[rb]); + } + t1 = tcg_temp_new_i32(); + tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); + tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); + tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); + tcg_temp_free_i32(t1); + + return true; +#endif +} + +TRANS_FLAGS(MEM_TLBIE, TLBIE, do_tlbie, false) From f1fc233a6709a6a08eeb9e41d8579a065fb3ad8f Mon Sep 17 00:00:00 2001 From: Leandro Lupori Date: Tue, 10 May 2022 13:23:26 -0300 Subject: [PATCH 03/13] target/ppc: Move tlbiel to decode tree Also decode RIC, PRS and R operands. --- target/ppc/insn32.decode | 1 + target/ppc/translate.c | 22 -------------------- target/ppc/translate/storage-ctrl-impl.c.inc | 15 ++++++++----- 3 files changed, 11 insertions(+), 27 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index fdfd24e8bdd17..79c38453fc4a9 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -717,3 +717,4 @@ RFEBB 010011-------------- . 0010010010 - @XL_s @X_tlbie ...... rs:5 - ric:2 prs:1 r:1 rb:5 .......... . &X_tlbie TLBIE 011111 ..... - .. . . ..... 0100110010 - @X_tlbie +TLBIEL 011111 ..... - .. . . ..... 0100010010 - @X_tlbie diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 379913e9408e8..3b6a02458c2d5 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -5399,26 +5399,6 @@ static void gen_tlbia(DisasContext *ctx) #endif /* defined(CONFIG_USER_ONLY) */ } -/* tlbiel */ -static void gen_tlbiel(DisasContext *ctx) -{ -#if defined(CONFIG_USER_ONLY) - GEN_PRIV; -#else - bool psr = (ctx->opcode >> 17) & 0x1; - - if (ctx->pr || (!ctx->hv && !psr && ctx->hr)) { - /* - * tlbiel is privileged except when PSR=0 and HR=1, making it - * hypervisor privileged. - */ - GEN_PRIV; - } - - gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); -#endif /* defined(CONFIG_USER_ONLY) */ -} - /* tlbsync */ static void gen_tlbsync(DisasContext *ctx) { @@ -6876,8 +6856,6 @@ GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), * XXX Those instructions will need to be handled differently for * different ISA versions */ -GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE), -GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300), GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), #if defined(TARGET_PPC64) GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI), diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc b/target/ppc/translate/storage-ctrl-impl.c.inc index e623731f69627..a7b65b0c4de5a 100644 --- a/target/ppc/translate/storage-ctrl-impl.c.inc +++ b/target/ppc/translate/storage-ctrl-impl.c.inc @@ -40,19 +40,19 @@ static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local) } if (ctx->pr) { - /* tlbie is privileged... */ + /* tlbie[l] is privileged... */ GEN_PRIV2(true); } else if (!ctx->hv) { - if (!ctx->gtse || (!prs && ctx->hr)) { + if ((!prs && ctx->hr) || (!local && !ctx->gtse)) { /* - * ... except when GTSE=0 or when PRS=0 and HR=1, making it - * hypervisor privileged. + * ... except when PRS=0 and HR=1, or when GTSE=0 for tlbie, + * making it hypervisor privileged. */ GEN_PRIV2(true); } } - if (NARROW_MODE(ctx)) { + if (!local && NARROW_MODE(ctx)) { TCGv t0 = tcg_temp_new(); tcg_gen_ext32u_tl(t0, cpu_gpr[rb]); gen_helper_tlbie(cpu_env, t0); @@ -60,6 +60,10 @@ static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local) } else { gen_helper_tlbie(cpu_env, cpu_gpr[rb]); } + + if (local) + return true; + t1 = tcg_temp_new_i32(); tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); @@ -71,3 +75,4 @@ static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local) } TRANS_FLAGS(MEM_TLBIE, TLBIE, do_tlbie, false) +TRANS_FLAGS(MEM_TLBIE, TLBIEL, do_tlbie, true) From 5047bd058d4e07aa65879d0997de1abd890c93d1 Mon Sep 17 00:00:00 2001 From: Leandro Lupori Date: Mon, 2 May 2022 15:58:24 -0300 Subject: [PATCH 04/13] target/ppc: Implement ISA 3.00 tlbie[l] This initial version supports the invalidation of one or all TLB entries. Flush by PID/LPID, or based in process/partition scope is not supported, because it would make using the generic QEMU TLB implementation hard. In these cases, all entries are flushed. --- target/ppc/helper.h | 18 +++ target/ppc/mmu_helper.c | 153 +++++++++++++++++++ target/ppc/translate/storage-ctrl-impl.c.inc | 15 ++ 3 files changed, 186 insertions(+) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index aa6773c4a5679..d000dbf7b8759 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -631,6 +631,24 @@ DEF_HELPER_FLAGS_1(tlbia, TCG_CALL_NO_RWG, void, env) DEF_HELPER_FLAGS_2(tlbie, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_2(tlbiva, TCG_CALL_NO_RWG, void, env, tl) #if defined(TARGET_PPC64) + +/* + * tlbie[l] helper flags + * + * RIC, PRS, R and local are passed as flags in the last argument. + */ +#define TLBIE_F_RIC_SHIFT 0 +#define TLBIE_F_PRS_SHIFT 2 +#define TLBIE_F_R_SHIFT 3 +#define TLBIE_F_LOCAL_SHIFT 4 + +#define TLBIE_F_RIC_MASK (3 << TLBIE_F_RIC_SHIFT) +#define TLBIE_F_PRS (1 << TLBIE_F_PRS_SHIFT) +#define TLBIE_F_R (1 << TLBIE_F_R_SHIFT) +#define TLBIE_F_LOCAL (1 << TLBIE_F_LOCAL_SHIFT) + +DEF_HELPER_FLAGS_4(tlbie_isa300, TCG_CALL_NO_RWG, void, \ + env, tl, tl, i32) DEF_HELPER_FLAGS_3(store_slb, TCG_CALL_NO_RWG, void, env, tl, tl) DEF_HELPER_2(load_slb_esid, tl, env, tl) DEF_HELPER_2(load_slb_vsid, tl, env, tl) diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index 15239dc95b514..1b03fc7c62302 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -429,6 +429,159 @@ void helper_tlbie(CPUPPCState *env, target_ulong addr) ppc_tlb_invalidate_one(env, addr); } +#if defined(TARGET_PPC64) + +/* Invalidation Selector */ +#define TLBIE_IS_VA 0 +#define TLBIE_IS_PID 1 +#define TLBIE_IS_LPID 2 +#define TLBIE_IS_ALL 3 + +/* Radix Invalidation Control */ +#define TLBIE_RIC_TLB 0 +#define TLBIE_RIC_PWC 1 +#define TLBIE_RIC_ALL 2 +#define TLBIE_RIC_GRP 3 + +/* Radix Actual Page sizes */ +#define TLBIE_R_AP_4K 0 +#define TLBIE_R_AP_64K 5 +#define TLBIE_R_AP_2M 1 +#define TLBIE_R_AP_1G 2 + +/* RB field masks */ +#define TLBIE_RB_EPN_MASK PPC_BITMASK(0, 51) +#define TLBIE_RB_IS_MASK PPC_BITMASK(52, 53) +#define TLBIE_RB_AP_MASK PPC_BITMASK(56, 58) + +void helper_tlbie_isa300(CPUPPCState *env, target_ulong rb, target_ulong rs, + uint32_t flags) +{ + unsigned ric = (flags & TLBIE_F_RIC_MASK) >> TLBIE_F_RIC_SHIFT; + /* + * With the exception of the checks for invalid instruction forms, + * PRS is currently ignored, because we don't know if a given TLB entry + * is process or partition scoped. + */ + bool prs = flags & TLBIE_F_PRS; + bool r = flags & TLBIE_F_R; + bool local = flags & TLBIE_F_LOCAL; + bool effR; + unsigned is = extract64(rb, PPC_BIT_NR(53), 2), set; + unsigned ap; /* actual page size */ + target_ulong addr, pgoffs_mask; + + qemu_log_mask(CPU_LOG_MMU, + "%s: local=%d addr=" TARGET_FMT_lx " ric=%u prs=%d r=%d is=%u\n", + __func__, local, rb & TARGET_PAGE_MASK, ric, prs, r, is); + + effR = FIELD_EX64(env->msr, MSR, HV) ? r : env->spr[SPR_LPCR] & LPCR_HR; + + /* Partial TLB invalidation is supported for Radix only for now. */ + if (!effR) { + goto inval_all; + } + + /* Check for invalid instruction forms (effR=1). */ + if (unlikely(ric == TLBIE_RIC_GRP || + ((ric == TLBIE_RIC_PWC || ric == TLBIE_RIC_ALL) && + is == TLBIE_IS_VA) || + (!prs && is == TLBIE_IS_PID))) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid instruction form: ric=%u prs=%d r=%d is=%u\n", + __func__, ric, prs, r, is); + goto invalid; + } + + /* We don't cache Page Walks. */ + if (ric == TLBIE_RIC_PWC) { + if (local) { + set = extract64(rb, PPC_BIT_NR(51), 12); + if (set != 0) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid set: %d\n", + __func__, set); + goto invalid; + } + } + return; + } + + /* + * Invalidation by LPID or PID is not supported, so fallback + * to full TLB flush in these cases. + */ + if (is != TLBIE_IS_VA) { + goto inval_all; + } + + /* + * The results of an attempt to invalidate a translation outside of + * quadrant 0 for Radix Tree translation (effR=1, RIC=0, PRS=1, IS=0, + * and EA 0:1 != 0b00) are boundedly undefined. + */ + if (unlikely(ric == TLBIE_RIC_TLB && prs && is == TLBIE_IS_VA && + (rb & R_EADDR_QUADRANT) != R_EADDR_QUADRANT0)) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: attempt to invalidate a translation outside of quadrant 0\n", + __func__); + goto inval_all; + } + + assert(is == TLBIE_IS_VA); + assert(ric == TLBIE_RIC_TLB || ric == TLBIE_RIC_ALL); + + ap = extract64(rb, PPC_BIT_NR(58), 3); + switch (ap) { + case TLBIE_R_AP_4K: + pgoffs_mask = 0xfffull; + break; + + case TLBIE_R_AP_64K: + pgoffs_mask = 0xffffull; + break; + + case TLBIE_R_AP_2M: + pgoffs_mask = 0x1fffffull; + break; + + case TLBIE_R_AP_1G: + pgoffs_mask = 0x3fffffffull; + break; + + default: + /* + * If the value specified in RS 0:31, RS 32:63, RB 54:55, RB 56:58, + * RB 44:51, or RB 56:63, when it is needed to perform the specified + * operation, is not supported by the implementation, the instruction + * is treated as if the instruction form were invalid. + */ + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid AP: %d\n", __func__, ap); + goto invalid; + } + + addr = rb & TLBIE_RB_EPN_MASK & ~pgoffs_mask; + + if (local) { + tlb_flush_page(env_cpu(env), addr); + } else { + tlb_flush_page_all_cpus(env_cpu(env), addr); + } + return; + +inval_all: + env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH; + if (!local) + env->tlb_need_flush |= TLB_NEED_GLOBAL_FLUSH; + return; + +invalid: + raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, + POWERPC_EXCP_INVAL | + POWERPC_EXCP_INVAL_INVAL, GETPC()); +} + +#endif + void helper_tlbiva(CPUPPCState *env, target_ulong addr) { /* tlbiva instruction only exists on BookE */ diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc b/target/ppc/translate/storage-ctrl-impl.c.inc index a7b65b0c4de5a..7cf6019776fa7 100644 --- a/target/ppc/translate/storage-ctrl-impl.c.inc +++ b/target/ppc/translate/storage-ctrl-impl.c.inc @@ -57,6 +57,21 @@ static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local) tcg_gen_ext32u_tl(t0, cpu_gpr[rb]); gen_helper_tlbie(cpu_env, t0); tcg_temp_free(t0); + +#if defined(TARGET_PPC64) + /* + * ISA 3.1B says that MSR SF must be 1 when this instruction is executed; + * otherwise the results are undefined. + */ + } else if (r) { + gen_helper_tlbie_isa300(cpu_env, cpu_gpr[rb], cpu_gpr[a->rs], + tcg_constant_i32(ric << TLBIE_F_RIC_SHIFT | + prs << TLBIE_F_PRS_SHIFT | + r << TLBIE_F_R_SHIFT | + local << TLBIE_F_LOCAL_SHIFT)); + return true; +#endif + } else { gen_helper_tlbie(cpu_env, cpu_gpr[rb]); } From c36372153c14b0ac9ed4388d9c6eeaf3bb666fa8 Mon Sep 17 00:00:00 2001 From: Lucas Coutinho Date: Thu, 19 May 2022 14:27:34 -0300 Subject: [PATCH 05/13] target/ppc: implement slbiag Implement the following PowerISA v3.0 instuction: slbiag: SLB Invalidate All Global X-form Move the following PowerISA v3.0 instuction to decodetree: slbie: SLB Invalidate Entry X-form slbieg: SLB Invalidate Entry Global X-form slbia: SLB Invalidate All X-form slbmte: SLB Move To Entry X-form slbmfev: SLB Move From Entry VSID X-form slbmfee: SLB Move From Entry ESID X-form slbfee: SLB Find Entry ESID slbsync: SLB Synchronize Signed-off-by: Lucas Coutinho --- target/ppc/helper.h | 1 + target/ppc/insn32.decode | 32 ++++ target/ppc/mmu-hash64.c | 40 ++++ target/ppc/translate.c | 127 +----------- target/ppc/translate/storage-ctrl-impl.c.inc | 192 +++++++++++++++++++ 5 files changed, 266 insertions(+), 126 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index d000dbf7b8759..d8d319337acc8 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -654,6 +654,7 @@ DEF_HELPER_2(load_slb_esid, tl, env, tl) DEF_HELPER_2(load_slb_vsid, tl, env, tl) DEF_HELPER_2(find_slb_vsid, tl, env, tl) DEF_HELPER_FLAGS_2(slbia, TCG_CALL_NO_RWG, void, env, i32) +DEF_HELPER_FLAGS_3(SLBIAG, TCG_CALL_NO_RWG, void, env, tl, i32) DEF_HELPER_FLAGS_2(slbie, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_2(slbieg, TCG_CALL_NO_RWG, void, env, tl) #endif diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 79c38453fc4a9..29f20c5b7a5d1 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -205,6 +205,21 @@ @Z23_te_tbp ...... ....0 te:5 ....0 rmc:2 ........ rc:1 &Z23_te_tb frt=%z23_frtp frb=%z23_frbp +&X_rs_l rs l:bool +@X_rs_l ...... rs:5 .... l:1 ..... .......... . &X_rs_l + +&X_ih ih:uint8_t +@X_ih ...... -- ih:3 ----- ----- .......... - &X_ih + +&X_rb rb +@X_rb ...... ----- ----- rb:5 .......... - &X_rb + +&X_sb rs rb +@X_sb ...... rs:5 ----- rb:5 .......... - &X_sb + +&X_tb1 rt rb +@X_tb1 ...... rt:5 ----- rb:5 .......... . &X_tb1 + ### Fixed-Point Load Instructions LBZ 100010 ..... ..... ................ @D @@ -711,6 +726,23 @@ XVTLSBB 111100 ... -- 00010 ..... 111011011 . - @XX2_bf_xb @XL_s ......-------------- s:1 .......... - &XL_s RFEBB 010011-------------- . 0010010010 - @XL_s +## SLB Management Instructions + +SLBIE 011111 ----- ----- ..... 0110110010 - @X_rb +SLBIEG 011111 ..... ----- ..... 0111010010 - @X_sb + +SLBIA 011111 --... ----- ----- 0111110010 - @X_ih +SLBIAG 011111 ..... ----. ----- 1101010010 - @X_rs_l + +SLBMTE 011111 ..... ----- ..... 0110010010 - @X_sb + +SLBMFEV 011111 ..... ----- ..... 1101010011 - @X_sb +SLBMFEE 011111 ..... ----- ..... 1110010011 - @X_sb + +SLBFEE 011111 ..... ----- ..... 1111010011 1 @X_tb1 + +SLBSYNC 011111 ----- ----- ----- 0101010010 - + ## TLB Management Instructions &X_tlbie rb rs ric prs:bool r:bool diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index da9fe99ff8bd4..f67ff95c35bdc 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -173,6 +173,46 @@ void helper_slbia(CPUPPCState *env, uint32_t ih) } } +#if defined(TARGET_PPC64) +void helper_SLBIAG(CPUPPCState *env, target_ulong rs, uint32_t l) +{ + PowerPCCPU *cpu = env_archcpu(env); + int starting_entry; + int n; + + /* + * slbia must always flush all TLB (which is equivalent to ERAT in ppc + * architecture). Matching on SLB_ESID_V is not good enough, because slbmte + * can overwrite a valid SLB without flushing its lookaside information. + * + * It would be possible to keep the TLB in synch with the SLB by flushing + * when a valid entry is overwritten by slbmte, and therefore slbia would + * not have to flush unless it evicts a valid SLB entry. However it is + * expected that slbmte is more common than slbia, and slbia is usually + * going to evict valid SLB entries, so that tradeoff is unlikely to be a + * good one. + * + */ + env->tlb_need_flush |= TLB_NEED_GLOBAL_FLUSH | TLB_NEED_LOCAL_FLUSH; + + for (n = 1; n < cpu->hash64_opts->slb_size; n++) { + ppc_slb_t *slb = &env->slb[n]; + + if (!(slb->esid & SLB_ESID_V)) { + continue; + } + if (env->mmu_model == POWERPC_MMU_3_00) { + if ((slb->vsid & SLB_VSID_C) == 0) { + /* preserves entries with a class value of 0 */ + continue; + } + } + + slb->esid &= ~SLB_ESID_V; + } +} +#endif + static void __helper_slbie(CPUPPCState *env, target_ulong addr, target_ulong global) { diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 3b6a02458c2d5..a04ff3350d4fc 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -5321,67 +5321,6 @@ static void gen_mtsrin_64b(DisasContext *ctx) #endif /* defined(CONFIG_USER_ONLY) */ } -/* slbmte */ -static void gen_slbmte(DisasContext *ctx) -{ -#if defined(CONFIG_USER_ONLY) - GEN_PRIV; -#else - CHK_SV; - - gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], - cpu_gpr[rS(ctx->opcode)]); -#endif /* defined(CONFIG_USER_ONLY) */ -} - -static void gen_slbmfee(DisasContext *ctx) -{ -#if defined(CONFIG_USER_ONLY) - GEN_PRIV; -#else - CHK_SV; - - gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, - cpu_gpr[rB(ctx->opcode)]); -#endif /* defined(CONFIG_USER_ONLY) */ -} - -static void gen_slbmfev(DisasContext *ctx) -{ -#if defined(CONFIG_USER_ONLY) - GEN_PRIV; -#else - CHK_SV; - - gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, - cpu_gpr[rB(ctx->opcode)]); -#endif /* defined(CONFIG_USER_ONLY) */ -} - -static void gen_slbfee_(DisasContext *ctx) -{ -#if defined(CONFIG_USER_ONLY) - gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); -#else - TCGLabel *l1, *l2; - - if (unlikely(ctx->pr)) { - gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); - return; - } - gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, - cpu_gpr[rB(ctx->opcode)]); - l1 = gen_new_label(); - l2 = gen_new_label(); - tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1); - tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); - tcg_gen_br(l2); - gen_set_label(l1); - tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0); - gen_set_label(l2); -#endif -} #endif /* defined(TARGET_PPC64) */ /*** Lookaside buffer management ***/ @@ -5419,60 +5358,6 @@ static void gen_tlbsync(DisasContext *ctx) #endif /* defined(CONFIG_USER_ONLY) */ } -#if defined(TARGET_PPC64) -/* slbia */ -static void gen_slbia(DisasContext *ctx) -{ -#if defined(CONFIG_USER_ONLY) - GEN_PRIV; -#else - uint32_t ih = (ctx->opcode >> 21) & 0x7; - TCGv_i32 t0 = tcg_const_i32(ih); - - CHK_SV; - - gen_helper_slbia(cpu_env, t0); - tcg_temp_free_i32(t0); -#endif /* defined(CONFIG_USER_ONLY) */ -} - -/* slbie */ -static void gen_slbie(DisasContext *ctx) -{ -#if defined(CONFIG_USER_ONLY) - GEN_PRIV; -#else - CHK_SV; - - gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); -#endif /* defined(CONFIG_USER_ONLY) */ -} - -/* slbieg */ -static void gen_slbieg(DisasContext *ctx) -{ -#if defined(CONFIG_USER_ONLY) - GEN_PRIV; -#else - CHK_SV; - - gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]); -#endif /* defined(CONFIG_USER_ONLY) */ -} - -/* slbsync */ -static void gen_slbsync(DisasContext *ctx) -{ -#if defined(CONFIG_USER_ONLY) - GEN_PRIV; -#else - CHK_SV; - gen_check_tlb_flush(ctx, true); -#endif /* defined(CONFIG_USER_ONLY) */ -} - -#endif /* defined(TARGET_PPC64) */ - /*** External control ***/ /* Optional: */ @@ -6551,7 +6436,7 @@ static int times_16(DisasContext *ctx, int x) */ #define TRANS(NAME, FUNC, ...) \ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ - { return FUNC(ctx, a, __VA_ARGS__); } + { return FUNC(ctx, a, ##__VA_ARGS__); } #define TRANS_FLAGS(FLAGS, NAME, FUNC, ...) \ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ { \ @@ -6846,10 +6731,6 @@ GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT_64B), -GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), -GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), -GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), -GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B), #endif GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), /* @@ -6857,12 +6738,6 @@ GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), * different ISA versions */ GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), -#if defined(TARGET_PPC64) -GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI), -GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), -GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300), -GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300), -#endif GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc b/target/ppc/translate/storage-ctrl-impl.c.inc index 7cf6019776fa7..f483a705042a0 100644 --- a/target/ppc/translate/storage-ctrl-impl.c.inc +++ b/target/ppc/translate/storage-ctrl-impl.c.inc @@ -21,6 +21,198 @@ * Store Control Instructions */ +static bool do_slbie(DisasContext *ctx, arg_X_rb *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS2(ctx, ISA300); + +#if defined(CONFIG_USER_ONLY) + GEN_PRIV2(true); +#else + +#if defined(TARGET_PPC64) + gen_helper_slbie(cpu_env, cpu_gpr[a->rb]); +#else + qemu_build_not_reached(); +#endif +#endif + return true; +} + +static bool do_slbieg(DisasContext *ctx, arg_X_sb *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS2(ctx, ISA300); + +#if defined(CONFIG_USER_ONLY) + GEN_PRIV2(true); +#else + +#if defined(TARGET_PPC64) + gen_helper_slbieg(cpu_env, cpu_gpr[a->rb]); +#else + qemu_build_not_reached(); +#endif +#endif + return true; +} + +static bool do_slbia(DisasContext *ctx, arg_X_ih *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS2(ctx, ISA300); + +#if defined(CONFIG_USER_ONLY) + GEN_PRIV2(true); +#else + +#if defined(TARGET_PPC64) + gen_helper_slbia(cpu_env, tcg_constant_i32(a->ih)); +#else + qemu_build_not_reached(); +#endif +#endif + return true; +} + +static bool do_slbiag(DisasContext *ctx, arg_X_rs_l *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS2(ctx, ISA300); + +#if defined(CONFIG_USER_ONLY) + GEN_PRIV2(true); +#else + +#if defined(TARGET_PPC64) + gen_helper_SLBIAG(cpu_env, cpu_gpr[a->rs], tcg_constant_i32(a->l)); +#else + qemu_build_not_reached(); +#endif +#endif + return true; +} + +static bool do_slbmte(DisasContext *ctx, arg_X_sb *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS2(ctx, ISA300); + +#if defined(CONFIG_USER_ONLY) + GEN_PRIV2(true); +#else + +#if defined(TARGET_PPC64) + gen_helper_store_slb(cpu_env, cpu_gpr[a->rb], cpu_gpr[a->rs]); +#else + qemu_build_not_reached(); +#endif +#endif + return true; +} + +static bool do_slbmfev(DisasContext *ctx, arg_X_sb *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS2(ctx, ISA300); + +#if defined(CONFIG_USER_ONLY) + GEN_PRIV2(true); +#else + +#if defined(TARGET_PPC64) + gen_helper_load_slb_vsid(cpu_gpr[a->rs], cpu_env, + cpu_gpr[a->rb]); +#else + qemu_build_not_reached(); +#endif +#endif + return true; +} + +static bool do_slbmfee(DisasContext *ctx, arg_X_sb *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS2(ctx, ISA300); + +#if defined(CONFIG_USER_ONLY) + GEN_PRIV2(true); +#else + +#if defined(TARGET_PPC64) + gen_helper_load_slb_esid(cpu_gpr[a->rs],cpu_env, cpu_gpr[a->rb]); +#else + qemu_build_not_reached(); +#endif +#endif + return true; +} + +static bool do_slbfee(DisasContext *ctx, arg_X_tb1 *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS2(ctx, ISA300); + +#if defined(CONFIG_USER_ONLY) + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); +#else + +#if defined(TARGET_PPC64) + TCGLabel *l1, *l2; + if (unlikely(ctx->pr)) { + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); + return true; + } + gen_helper_find_slb_vsid(cpu_gpr[a->rt], cpu_env, + cpu_gpr[a->rb]); + l1 = gen_new_label(); + l2 = gen_new_label(); + tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[a->rt], -1, l1); + tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); + tcg_gen_br(l2); + gen_set_label(l1); + tcg_gen_movi_tl(cpu_gpr[a->rt], 0); + gen_set_label(l2); +#else + qemu_build_not_reached(); +#endif +#endif + return true; +} + +static bool do_slbsync(DisasContext *ctx) +{ + REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS2(ctx, ISA300); + +#if defined(CONFIG_USER_ONLY) + GEN_PRIV2(true); +#else + +#if defined(TARGET_PPC64) + gen_check_tlb_flush(ctx, true); +#else + qemu_build_not_reached(); +#endif +#endif + return true; +} + +TRANS(SLBIE, do_slbie) +TRANS(SLBIEG, do_slbieg) +TRANS(SLBIA, do_slbia) +TRANS(SLBIAG, do_slbiag) +TRANS(SLBMTE, do_slbmte) +TRANS(SLBMFEV, do_slbmfev) +TRANS(SLBMFEE, do_slbmfee) +TRANS(SLBFEE, do_slbfee) + +static bool trans_SLBSYNC(DisasContext *ctx, arg_SLBSYNC *a) +{ + return do_slbsync(ctx); +} + static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local) { #if defined(CONFIG_USER_ONLY) From b432d649b00e8e0ce811c44c23a5483d3494865c Mon Sep 17 00:00:00 2001 From: Lucas Coutinho Date: Thu, 19 May 2022 15:13:30 -0300 Subject: [PATCH 06/13] Remove unused variable --- target/ppc/mmu-hash64.c | 1 - 1 file changed, 1 deletion(-) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index f67ff95c35bdc..9687322f7b0d1 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -177,7 +177,6 @@ void helper_slbia(CPUPPCState *env, uint32_t ih) void helper_SLBIAG(CPUPPCState *env, target_ulong rs, uint32_t l) { PowerPCCPU *cpu = env_archcpu(env); - int starting_entry; int n; /* From 78550631d0cd99cd496867b5b71bc91a9e7f7b7e Mon Sep 17 00:00:00 2001 From: Lucas Coutinho Date: Thu, 26 May 2022 16:05:04 -0300 Subject: [PATCH 07/13] target/ppc: Reusing previously types declaration in insn32.decode --- target/ppc/insn32.decode | 20 +++++++------------- target/ppc/translate/storage-ctrl-impl.c.inc | 16 ++++++++-------- 2 files changed, 15 insertions(+), 21 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 29f20c5b7a5d1..21da5cb0c4d6a 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -209,16 +209,10 @@ @X_rs_l ...... rs:5 .... l:1 ..... .......... . &X_rs_l &X_ih ih:uint8_t -@X_ih ...... -- ih:3 ----- ----- .......... - &X_ih +@X_ih ...... .. ih:3 ..... ..... .......... . &X_ih &X_rb rb -@X_rb ...... ----- ----- rb:5 .......... - &X_rb - -&X_sb rs rb -@X_sb ...... rs:5 ----- rb:5 .......... - &X_sb - -&X_tb1 rt rb -@X_tb1 ...... rt:5 ----- rb:5 .......... . &X_tb1 +@X_rb ...... ..... ..... rb:5 .......... . &X_rb ### Fixed-Point Load Instructions @@ -729,17 +723,17 @@ RFEBB 010011-------------- . 0010010010 - @XL_s ## SLB Management Instructions SLBIE 011111 ----- ----- ..... 0110110010 - @X_rb -SLBIEG 011111 ..... ----- ..... 0111010010 - @X_sb +SLBIEG 011111 ..... ----- ..... 0111010010 - @X_tb SLBIA 011111 --... ----- ----- 0111110010 - @X_ih SLBIAG 011111 ..... ----. ----- 1101010010 - @X_rs_l -SLBMTE 011111 ..... ----- ..... 0110010010 - @X_sb +SLBMTE 011111 ..... ----- ..... 0110010010 - @X_tb -SLBMFEV 011111 ..... ----- ..... 1101010011 - @X_sb -SLBMFEE 011111 ..... ----- ..... 1110010011 - @X_sb +SLBMFEV 011111 ..... ----- ..... 1101010011 - @X_tb +SLBMFEE 011111 ..... ----- ..... 1110010011 - @X_tb -SLBFEE 011111 ..... ----- ..... 1111010011 1 @X_tb1 +SLBFEE 011111 ..... ----- ..... 1111010011 1 @X_tb SLBSYNC 011111 ----- ----- ----- 0101010010 - diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc b/target/ppc/translate/storage-ctrl-impl.c.inc index f483a705042a0..d46ad5bbeb06b 100644 --- a/target/ppc/translate/storage-ctrl-impl.c.inc +++ b/target/ppc/translate/storage-ctrl-impl.c.inc @@ -39,7 +39,7 @@ static bool do_slbie(DisasContext *ctx, arg_X_rb *a) return true; } -static bool do_slbieg(DisasContext *ctx, arg_X_sb *a) +static bool do_slbieg(DisasContext *ctx, arg_X_tb *a) { REQUIRE_64BIT(ctx); REQUIRE_INSNS_FLAGS2(ctx, ISA300); @@ -93,7 +93,7 @@ static bool do_slbiag(DisasContext *ctx, arg_X_rs_l *a) return true; } -static bool do_slbmte(DisasContext *ctx, arg_X_sb *a) +static bool do_slbmte(DisasContext *ctx, arg_X_tb *a) { REQUIRE_64BIT(ctx); REQUIRE_INSNS_FLAGS2(ctx, ISA300); @@ -103,7 +103,7 @@ static bool do_slbmte(DisasContext *ctx, arg_X_sb *a) #else #if defined(TARGET_PPC64) - gen_helper_store_slb(cpu_env, cpu_gpr[a->rb], cpu_gpr[a->rs]); + gen_helper_store_slb(cpu_env, cpu_gpr[a->rb], cpu_gpr[a->rt]); #else qemu_build_not_reached(); #endif @@ -111,7 +111,7 @@ static bool do_slbmte(DisasContext *ctx, arg_X_sb *a) return true; } -static bool do_slbmfev(DisasContext *ctx, arg_X_sb *a) +static bool do_slbmfev(DisasContext *ctx, arg_X_tb *a) { REQUIRE_64BIT(ctx); REQUIRE_INSNS_FLAGS2(ctx, ISA300); @@ -121,7 +121,7 @@ static bool do_slbmfev(DisasContext *ctx, arg_X_sb *a) #else #if defined(TARGET_PPC64) - gen_helper_load_slb_vsid(cpu_gpr[a->rs], cpu_env, + gen_helper_load_slb_vsid(cpu_gpr[a->rt], cpu_env, cpu_gpr[a->rb]); #else qemu_build_not_reached(); @@ -130,7 +130,7 @@ static bool do_slbmfev(DisasContext *ctx, arg_X_sb *a) return true; } -static bool do_slbmfee(DisasContext *ctx, arg_X_sb *a) +static bool do_slbmfee(DisasContext *ctx, arg_X_tb *a) { REQUIRE_64BIT(ctx); REQUIRE_INSNS_FLAGS2(ctx, ISA300); @@ -140,7 +140,7 @@ static bool do_slbmfee(DisasContext *ctx, arg_X_sb *a) #else #if defined(TARGET_PPC64) - gen_helper_load_slb_esid(cpu_gpr[a->rs],cpu_env, cpu_gpr[a->rb]); + gen_helper_load_slb_esid(cpu_gpr[a->rt],cpu_env, cpu_gpr[a->rb]); #else qemu_build_not_reached(); #endif @@ -148,7 +148,7 @@ static bool do_slbmfee(DisasContext *ctx, arg_X_sb *a) return true; } -static bool do_slbfee(DisasContext *ctx, arg_X_tb1 *a) +static bool do_slbfee(DisasContext *ctx, arg_X_tb *a) { REQUIRE_64BIT(ctx); REQUIRE_INSNS_FLAGS2(ctx, ISA300); From a33758a2d80dbf407c21657a2ccd0b0f68ee3f62 Mon Sep 17 00:00:00 2001 From: Lucas Coutinho Date: Fri, 27 May 2022 09:03:38 -0300 Subject: [PATCH 08/13] target/ppc: Fix slbiag --- target/ppc/mmu-hash64.c | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 9687322f7b0d1..874f49d779039 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -180,7 +180,7 @@ void helper_SLBIAG(CPUPPCState *env, target_ulong rs, uint32_t l) int n; /* - * slbia must always flush all TLB (which is equivalent to ERAT in ppc + * slbiag must always flush all TLB (which is equivalent to ERAT in ppc * architecture). Matching on SLB_ESID_V is not good enough, because slbmte * can overwrite a valid SLB without flushing its lookaside information. * @@ -190,22 +190,15 @@ void helper_SLBIAG(CPUPPCState *env, target_ulong rs, uint32_t l) * expected that slbmte is more common than slbia, and slbia is usually * going to evict valid SLB entries, so that tradeoff is unlikely to be a * good one. - * */ - env->tlb_need_flush |= TLB_NEED_GLOBAL_FLUSH | TLB_NEED_LOCAL_FLUSH; + env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH; - for (n = 1; n < cpu->hash64_opts->slb_size; n++) { + for (n = 0; n < cpu->hash64_opts->slb_size; n++) { ppc_slb_t *slb = &env->slb[n]; if (!(slb->esid & SLB_ESID_V)) { continue; } - if (env->mmu_model == POWERPC_MMU_3_00) { - if ((slb->vsid & SLB_VSID_C) == 0) { - /* preserves entries with a class value of 0 */ - continue; - } - } slb->esid &= ~SLB_ESID_V; } From 1a0d54c2ac9efc7ff4c54be7871804f242cc1ea8 Mon Sep 17 00:00:00 2001 From: Lucas Coutinho Date: Fri, 27 May 2022 14:21:51 -0300 Subject: [PATCH 09/13] target/ppc: Remove uses of macro TRANS --- target/ppc/translate.c | 2 +- target/ppc/translate/storage-ctrl-impl.c.inc | 49 ++++++++++++++++---- 2 files changed, 41 insertions(+), 10 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index a04ff3350d4fc..d5052c81d5c76 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -6436,7 +6436,7 @@ static int times_16(DisasContext *ctx, int x) */ #define TRANS(NAME, FUNC, ...) \ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ - { return FUNC(ctx, a, ##__VA_ARGS__); } + { return FUNC(ctx, a, __VA_ARGS__); } #define TRANS_FLAGS(FLAGS, NAME, FUNC, ...) \ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ { \ diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc b/target/ppc/translate/storage-ctrl-impl.c.inc index d46ad5bbeb06b..38b11ff956320 100644 --- a/target/ppc/translate/storage-ctrl-impl.c.inc +++ b/target/ppc/translate/storage-ctrl-impl.c.inc @@ -159,6 +159,7 @@ static bool do_slbfee(DisasContext *ctx, arg_X_tb *a) #if defined(TARGET_PPC64) TCGLabel *l1, *l2; + if (unlikely(ctx->pr)) { gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); return true; @@ -185,7 +186,6 @@ static bool do_slbsync(DisasContext *ctx) { REQUIRE_64BIT(ctx); REQUIRE_INSNS_FLAGS2(ctx, ISA300); - #if defined(CONFIG_USER_ONLY) GEN_PRIV2(true); #else @@ -199,14 +199,45 @@ static bool do_slbsync(DisasContext *ctx) return true; } -TRANS(SLBIE, do_slbie) -TRANS(SLBIEG, do_slbieg) -TRANS(SLBIA, do_slbia) -TRANS(SLBIAG, do_slbiag) -TRANS(SLBMTE, do_slbmte) -TRANS(SLBMFEV, do_slbmfev) -TRANS(SLBMFEE, do_slbmfee) -TRANS(SLBFEE, do_slbfee) +static bool trans_SLBIE(DisasContext *ctx, arg_SLBIE *a) +{ + return do_slbie(ctx, a); +} + +static bool trans_SLBIEG(DisasContext *ctx, arg_SLBIEG *a) +{ + return do_slbieg(ctx, a); +} + +static bool trans_SLBIA(DisasContext *ctx, arg_SLBIA *a) +{ + return do_slbia(ctx, a); +} + +static bool trans_SLBIAG(DisasContext *ctx, arg_SLBIAG *a) +{ + return do_slbiag(ctx, a); +} + +static bool trans_SLBMTE(DisasContext *ctx, arg_SLBMTE *a) +{ + return do_slbmte(ctx, a); +} + +static bool trans_SLBMFEV(DisasContext *ctx, arg_SLBMFEV *a) +{ + return do_slbmfev(ctx, a); +} + +static bool trans_SLBMFEE(DisasContext *ctx, arg_SLBMFEE *a) +{ + return do_slbmfee(ctx, a); +} + +static bool trans_SLBFEE(DisasContext *ctx, arg_SLBFEE *a) +{ + return do_slbfee(ctx, a); +} static bool trans_SLBSYNC(DisasContext *ctx, arg_SLBSYNC *a) { From 4f51cb352ac4dc1718ddd2fb0a3cf81d31705db1 Mon Sep 17 00:00:00 2001 From: Lucas Coutinho Date: Mon, 30 May 2022 09:19:05 -0300 Subject: [PATCH 10/13] Add missing flags check --- target/ppc/translate.c | 277 +++++++++---------- target/ppc/translate/fp-impl.c.inc | 4 +- target/ppc/translate/storage-ctrl-impl.c.inc | 38 ++- 3 files changed, 164 insertions(+), 155 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index d5052c81d5c76..1f6cdd2a6763b 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -1268,43 +1268,38 @@ typedef struct opcode_t { } opcode_t; /* Helpers for priv. check */ -#define GEN_PRIV \ - do { \ - gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \ - } while (0) - -#define GEN_PRIV2(ret) \ - do { \ - gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ - return (ret); \ +#define GEN_PRIV(CTX, ...) \ + do { \ + gen_priv_exception(CTX, POWERPC_EXCP_PRIV_OPC); \ + return __VA_ARGS__; \ } while (0) #if defined(CONFIG_USER_ONLY) -#define CHK_HV GEN_PRIV -#define CHK_SV GEN_PRIV -#define CHK_HVRM GEN_PRIV +#define CHK_HV(CTX, ...) GEN_PRIV(CTX, __VA_ARGS__) +#define CHK_SV(CTX, ...) GEN_PRIV(CTX, __VA_ARGS__) +#define CHK_HVRM(CTX, ...) GEN_PRIV(CTX, __VA_ARGS__) #else -#define CHK_HV \ - do { \ - if (unlikely(ctx->pr || !ctx->hv)) { \ - GEN_PRIV; \ - } \ +#define CHK_HV(CTX, ...) \ + do { \ + if (unlikely((CTX)->pr || !(CTX)->hv)) {\ + GEN_PRIV(CTX, __VA_ARGS__); \ + } \ } while (0) -#define CHK_SV \ - do { \ - if (unlikely(ctx->pr)) { \ - GEN_PRIV; \ - } \ +#define CHK_SV(CTX, ...) \ + do { \ + if (unlikely((CTX)->pr)) { \ + GEN_PRIV(CTX, __VA_ARGS__); \ + } \ } while (0) -#define CHK_HVRM \ - do { \ - if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ - GEN_PRIV; \ - } \ +#define CHK_HVRM(CTX, ...) \ + do { \ + if (unlikely((CTX)->pr || !(CTX)->hv || (CTX)->dr)) { \ + GEN_PRIV(CTX, __VA_ARGS__); \ + } \ } while (0) #endif -#define CHK_NONE +#define CHK_NONE(CTX, ...) /*****************************************************************************/ /* PowerPC instructions table */ @@ -3258,7 +3253,7 @@ GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_UQ)) static void glue(gen_, name##x)(DisasContext *ctx) \ { \ TCGv EA; \ - chk; \ + chk(ctx); \ gen_set_access_type(ctx, ACCESS_INT); \ EA = tcg_temp_new(); \ gen_addr_reg_index(ctx, EA); \ @@ -3276,7 +3271,7 @@ static void glue(gen_, name##x)(DisasContext *ctx) \ static void glue(gen_, name##epx)(DisasContext *ctx) \ { \ TCGv EA; \ - CHK_SV; \ + CHK_SV(ctx); \ gen_set_access_type(ctx, ACCESS_INT); \ EA = tcg_temp_new(); \ gen_addr_reg_index(ctx, EA); \ @@ -3304,7 +3299,7 @@ GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) static void glue(gen_, name##x)(DisasContext *ctx) \ { \ TCGv EA; \ - chk; \ + chk(ctx); \ gen_set_access_type(ctx, ACCESS_INT); \ EA = tcg_temp_new(); \ gen_addr_reg_index(ctx, EA); \ @@ -3321,7 +3316,7 @@ static void glue(gen_, name##x)(DisasContext *ctx) \ static void glue(gen_, name##epx)(DisasContext *ctx) \ { \ TCGv EA; \ - CHK_SV; \ + CHK_SV(ctx); \ gen_set_access_type(ctx, ACCESS_INT); \ EA = tcg_temp_new(); \ gen_addr_reg_index(ctx, EA); \ @@ -4053,11 +4048,11 @@ static void gen_wait(DisasContext *ctx) static void gen_doze(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else TCGv_i32 t; - CHK_HV; + CHK_HV(ctx); t = tcg_const_i32(PPC_PM_DOZE); gen_helper_pminsn(cpu_env, t); tcg_temp_free_i32(t); @@ -4069,11 +4064,11 @@ static void gen_doze(DisasContext *ctx) static void gen_nap(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else TCGv_i32 t; - CHK_HV; + CHK_HV(ctx); t = tcg_const_i32(PPC_PM_NAP); gen_helper_pminsn(cpu_env, t); tcg_temp_free_i32(t); @@ -4085,11 +4080,11 @@ static void gen_nap(DisasContext *ctx) static void gen_stop(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else TCGv_i32 t; - CHK_HV; + CHK_HV(ctx); t = tcg_const_i32(PPC_PM_STOP); gen_helper_pminsn(cpu_env, t); tcg_temp_free_i32(t); @@ -4101,11 +4096,11 @@ static void gen_stop(DisasContext *ctx) static void gen_sleep(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else TCGv_i32 t; - CHK_HV; + CHK_HV(ctx); t = tcg_const_i32(PPC_PM_SLEEP); gen_helper_pminsn(cpu_env, t); tcg_temp_free_i32(t); @@ -4117,11 +4112,11 @@ static void gen_sleep(DisasContext *ctx) static void gen_rvwinkle(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else TCGv_i32 t; - CHK_HV; + CHK_HV(ctx); t = tcg_const_i32(PPC_PM_RVWINKLE); gen_helper_pminsn(cpu_env, t); tcg_temp_free_i32(t); @@ -4451,7 +4446,7 @@ static void gen_mcrf(DisasContext *ctx) static void gen_rfi(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else /* * This instruction doesn't exist anymore on 64-bit server @@ -4462,7 +4457,7 @@ static void gen_rfi(DisasContext *ctx) return; } /* Restore CPU state */ - CHK_SV; + CHK_SV(ctx); gen_icount_io_start(ctx); gen_update_cfar(ctx, ctx->cia); gen_helper_rfi(cpu_env); @@ -4474,10 +4469,10 @@ static void gen_rfi(DisasContext *ctx) static void gen_rfid(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else /* Restore CPU state */ - CHK_SV; + CHK_SV(ctx); gen_icount_io_start(ctx); gen_update_cfar(ctx, ctx->cia); gen_helper_rfid(cpu_env); @@ -4489,10 +4484,10 @@ static void gen_rfid(DisasContext *ctx) static void gen_rfscv(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else /* Restore CPU state */ - CHK_SV; + CHK_SV(ctx); gen_icount_io_start(ctx); gen_update_cfar(ctx, ctx->cia); gen_helper_rfscv(cpu_env); @@ -4504,10 +4499,10 @@ static void gen_rfscv(DisasContext *ctx) static void gen_hrfid(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else /* Restore CPU state */ - CHK_HV; + CHK_HV(ctx); gen_helper_hrfid(cpu_env); ctx->base.is_jmp = DISAS_EXIT; #endif @@ -4708,7 +4703,7 @@ static void gen_mfcr(DisasContext *ctx) /* mfmsr */ static void gen_mfmsr(DisasContext *ctx) { - CHK_SV; + CHK_SV(ctx); tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); } @@ -4822,7 +4817,7 @@ static void gen_mtmsrd(DisasContext *ctx) return; } - CHK_SV; + CHK_SV(ctx); #if !defined(CONFIG_USER_ONLY) TCGv t0, t1; @@ -4865,7 +4860,7 @@ static void gen_mtmsrd(DisasContext *ctx) static void gen_mtmsr(DisasContext *ctx) { - CHK_SV; + CHK_SV(ctx); #if !defined(CONFIG_USER_ONLY) TCGv t0, t1; @@ -4997,7 +4992,7 @@ static void gen_dcbfep(DisasContext *ctx) { /* XXX: specification says this is treated as a load by the MMU */ TCGv t0; - CHK_SV; + CHK_SV(ctx); gen_set_access_type(ctx, ACCESS_CACHE); t0 = tcg_temp_new(); gen_addr_reg_index(ctx, t0); @@ -5009,11 +5004,11 @@ static void gen_dcbfep(DisasContext *ctx) static void gen_dcbi(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else TCGv EA, val; - CHK_SV; + CHK_SV(ctx); EA = tcg_temp_new(); gen_set_access_type(ctx, ACCESS_CACHE); gen_addr_reg_index(ctx, EA); @@ -5198,11 +5193,11 @@ static void gen_dcba(DisasContext *ctx) static void gen_mfsr(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else TCGv t0; - CHK_SV; + CHK_SV(ctx); t0 = tcg_const_tl(SR(ctx->opcode)); gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); tcg_temp_free(t0); @@ -5213,11 +5208,11 @@ static void gen_mfsr(DisasContext *ctx) static void gen_mfsrin(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else TCGv t0; - CHK_SV; + CHK_SV(ctx); t0 = tcg_temp_new(); tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); @@ -5229,11 +5224,11 @@ static void gen_mfsrin(DisasContext *ctx) static void gen_mtsr(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else TCGv t0; - CHK_SV; + CHK_SV(ctx); t0 = tcg_const_tl(SR(ctx->opcode)); gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); tcg_temp_free(t0); @@ -5244,10 +5239,10 @@ static void gen_mtsr(DisasContext *ctx) static void gen_mtsrin(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else TCGv t0; - CHK_SV; + CHK_SV(ctx); t0 = tcg_temp_new(); tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); @@ -5263,11 +5258,11 @@ static void gen_mtsrin(DisasContext *ctx) static void gen_mfsr_64b(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else TCGv t0; - CHK_SV; + CHK_SV(ctx); t0 = tcg_const_tl(SR(ctx->opcode)); gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); tcg_temp_free(t0); @@ -5278,11 +5273,11 @@ static void gen_mfsr_64b(DisasContext *ctx) static void gen_mfsrin_64b(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else TCGv t0; - CHK_SV; + CHK_SV(ctx); t0 = tcg_temp_new(); tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); @@ -5294,11 +5289,11 @@ static void gen_mfsrin_64b(DisasContext *ctx) static void gen_mtsr_64b(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else TCGv t0; - CHK_SV; + CHK_SV(ctx); t0 = tcg_const_tl(SR(ctx->opcode)); gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); tcg_temp_free(t0); @@ -5309,11 +5304,11 @@ static void gen_mtsr_64b(DisasContext *ctx) static void gen_mtsrin_64b(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else TCGv t0; - CHK_SV; + CHK_SV(ctx); t0 = tcg_temp_new(); tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); @@ -5330,9 +5325,9 @@ static void gen_mtsrin_64b(DisasContext *ctx) static void gen_tlbia(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else - CHK_HV; + CHK_HV(ctx); gen_helper_tlbia(cpu_env); #endif /* defined(CONFIG_USER_ONLY) */ @@ -5342,13 +5337,13 @@ static void gen_tlbia(DisasContext *ctx) static void gen_tlbsync(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else if (ctx->gtse) { - CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */ + CHK_SV(ctx); /* If gtse is set then tlbsync is supervisor privileged */ } else { - CHK_HV; /* Else hypervisor privileged */ + CHK_HV(ctx); /* Else hypervisor privileged */ } /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ @@ -5393,9 +5388,9 @@ static void gen_ecowx(DisasContext *ctx) static void gen_tlbld_6xx(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else - CHK_SV; + CHK_SV(ctx); gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); #endif /* defined(CONFIG_USER_ONLY) */ } @@ -5404,9 +5399,9 @@ static void gen_tlbld_6xx(DisasContext *ctx) static void gen_tlbli_6xx(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else - CHK_SV; + CHK_SV(ctx); gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); #endif /* defined(CONFIG_USER_ONLY) */ } @@ -5424,11 +5419,11 @@ static void gen_mfapidi(DisasContext *ctx) static void gen_tlbiva(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else TCGv t0; - CHK_SV; + CHK_SV(ctx); t0 = tcg_temp_new(); gen_addr_reg_index(ctx, t0); gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); @@ -5655,11 +5650,11 @@ GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); static void gen_mfdcr(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else TCGv dcrn; - CHK_SV; + CHK_SV(ctx); dcrn = tcg_const_tl(SPR(ctx->opcode)); gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); tcg_temp_free(dcrn); @@ -5670,11 +5665,11 @@ static void gen_mfdcr(DisasContext *ctx) static void gen_mtdcr(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else TCGv dcrn; - CHK_SV; + CHK_SV(ctx); dcrn = tcg_const_tl(SPR(ctx->opcode)); gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); tcg_temp_free(dcrn); @@ -5686,9 +5681,9 @@ static void gen_mtdcr(DisasContext *ctx) static void gen_mfdcrx(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else - CHK_SV; + CHK_SV(ctx); gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)]); /* Note: Rc update flag set leads to undefined state of Rc0 */ @@ -5700,9 +5695,9 @@ static void gen_mfdcrx(DisasContext *ctx) static void gen_mtdcrx(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else - CHK_SV; + CHK_SV(ctx); gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); /* Note: Rc update flag set leads to undefined state of Rc0 */ @@ -5728,7 +5723,7 @@ static void gen_mtdcrux(DisasContext *ctx) /* dccci */ static void gen_dccci(DisasContext *ctx) { - CHK_SV; + CHK_SV(ctx); /* interpreted as no-op */ } @@ -5736,11 +5731,11 @@ static void gen_dccci(DisasContext *ctx) static void gen_dcread(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else TCGv EA, val; - CHK_SV; + CHK_SV(ctx); gen_set_access_type(ctx, ACCESS_CACHE); EA = tcg_temp_new(); gen_addr_reg_index(ctx, EA); @@ -5765,14 +5760,14 @@ static void gen_icbt_40x(DisasContext *ctx) /* iccci */ static void gen_iccci(DisasContext *ctx) { - CHK_SV; + CHK_SV(ctx); /* interpreted as no-op */ } /* icread */ static void gen_icread(DisasContext *ctx) { - CHK_SV; + CHK_SV(ctx); /* interpreted as no-op */ } @@ -5780,9 +5775,9 @@ static void gen_icread(DisasContext *ctx) static void gen_rfci_40x(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else - CHK_SV; + CHK_SV(ctx); /* Restore CPU state */ gen_helper_40x_rfci(cpu_env); ctx->base.is_jmp = DISAS_EXIT; @@ -5792,9 +5787,9 @@ static void gen_rfci_40x(DisasContext *ctx) static void gen_rfci(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else - CHK_SV; + CHK_SV(ctx); /* Restore CPU state */ gen_helper_rfci(cpu_env); ctx->base.is_jmp = DISAS_EXIT; @@ -5807,9 +5802,9 @@ static void gen_rfci(DisasContext *ctx) static void gen_rfdi(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else - CHK_SV; + CHK_SV(ctx); /* Restore CPU state */ gen_helper_rfdi(cpu_env); ctx->base.is_jmp = DISAS_EXIT; @@ -5820,9 +5815,9 @@ static void gen_rfdi(DisasContext *ctx) static void gen_rfmci(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else - CHK_SV; + CHK_SV(ctx); /* Restore CPU state */ gen_helper_rfmci(cpu_env); ctx->base.is_jmp = DISAS_EXIT; @@ -5835,9 +5830,9 @@ static void gen_rfmci(DisasContext *ctx) static void gen_tlbre_40x(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else - CHK_SV; + CHK_SV(ctx); switch (rB(ctx->opcode)) { case 0: gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, @@ -5858,11 +5853,11 @@ static void gen_tlbre_40x(DisasContext *ctx) static void gen_tlbsx_40x(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else TCGv t0; - CHK_SV; + CHK_SV(ctx); t0 = tcg_temp_new(); gen_addr_reg_index(ctx, t0); gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); @@ -5881,9 +5876,9 @@ static void gen_tlbsx_40x(DisasContext *ctx) static void gen_tlbwe_40x(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else - CHK_SV; + CHK_SV(ctx); switch (rB(ctx->opcode)) { case 0: @@ -5907,9 +5902,9 @@ static void gen_tlbwe_40x(DisasContext *ctx) static void gen_tlbre_440(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else - CHK_SV; + CHK_SV(ctx); switch (rB(ctx->opcode)) { case 0: @@ -5933,11 +5928,11 @@ static void gen_tlbre_440(DisasContext *ctx) static void gen_tlbsx_440(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else TCGv t0; - CHK_SV; + CHK_SV(ctx); t0 = tcg_temp_new(); gen_addr_reg_index(ctx, t0); gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); @@ -5956,9 +5951,9 @@ static void gen_tlbsx_440(DisasContext *ctx) static void gen_tlbwe_440(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else - CHK_SV; + CHK_SV(ctx); switch (rB(ctx->opcode)) { case 0: case 1: @@ -5983,9 +5978,9 @@ static void gen_tlbwe_440(DisasContext *ctx) static void gen_tlbre_booke206(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else - CHK_SV; + CHK_SV(ctx); gen_helper_booke206_tlbre(cpu_env); #endif /* defined(CONFIG_USER_ONLY) */ } @@ -5994,11 +5989,11 @@ static void gen_tlbre_booke206(DisasContext *ctx) static void gen_tlbsx_booke206(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else TCGv t0; - CHK_SV; + CHK_SV(ctx); if (rA(ctx->opcode)) { t0 = tcg_temp_new(); tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); @@ -6016,9 +6011,9 @@ static void gen_tlbsx_booke206(DisasContext *ctx) static void gen_tlbwe_booke206(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else - CHK_SV; + CHK_SV(ctx); gen_helper_booke206_tlbwe(cpu_env); #endif /* defined(CONFIG_USER_ONLY) */ } @@ -6026,11 +6021,11 @@ static void gen_tlbwe_booke206(DisasContext *ctx) static void gen_tlbivax_booke206(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else TCGv t0; - CHK_SV; + CHK_SV(ctx); t0 = tcg_temp_new(); gen_addr_reg_index(ctx, t0); gen_helper_booke206_tlbivax(cpu_env, t0); @@ -6041,11 +6036,11 @@ static void gen_tlbivax_booke206(DisasContext *ctx) static void gen_tlbilx_booke206(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else TCGv t0; - CHK_SV; + CHK_SV(ctx); t0 = tcg_temp_new(); gen_addr_reg_index(ctx, t0); @@ -6073,11 +6068,11 @@ static void gen_tlbilx_booke206(DisasContext *ctx) static void gen_wrtee(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else TCGv t0; - CHK_SV; + CHK_SV(ctx); t0 = tcg_temp_new(); tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); @@ -6095,9 +6090,9 @@ static void gen_wrtee(DisasContext *ctx) static void gen_wrteei(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else - CHK_SV; + CHK_SV(ctx); if (ctx->opcode & 0x00008000) { tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); /* Stop translation to have a chance to raise an exception */ @@ -6151,9 +6146,9 @@ static void gen_icbt_440(DisasContext *ctx) static void gen_msgclr(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else - CHK_HV; + CHK_HV(ctx); if (is_book3s_arch2x(ctx)) { gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); } else { @@ -6165,9 +6160,9 @@ static void gen_msgclr(DisasContext *ctx) static void gen_msgsnd(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else - CHK_HV; + CHK_HV(ctx); if (is_book3s_arch2x(ctx)) { gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]); } else { @@ -6180,9 +6175,9 @@ static void gen_msgsnd(DisasContext *ctx) static void gen_msgclrp(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else - CHK_SV; + CHK_SV(ctx); gen_helper_book3s_msgclrp(cpu_env, cpu_gpr[rB(ctx->opcode)]); #endif /* defined(CONFIG_USER_ONLY) */ } @@ -6190,9 +6185,9 @@ static void gen_msgclrp(DisasContext *ctx) static void gen_msgsndp(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else - CHK_SV; + CHK_SV(ctx); gen_helper_book3s_msgsndp(cpu_env, cpu_gpr[rB(ctx->opcode)]); #endif /* defined(CONFIG_USER_ONLY) */ } @@ -6201,9 +6196,9 @@ static void gen_msgsndp(DisasContext *ctx) static void gen_msgsync(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV; + GEN_PRIV(ctx); #else - CHK_HV; + CHK_HV(ctx); #endif /* defined(CONFIG_USER_ONLY) */ /* interpreted as no-op */ } @@ -6322,7 +6317,7 @@ static inline void gen_##name(DisasContext *ctx) \ #define GEN_TM_PRIV_NOOP(name) \ static inline void gen_##name(DisasContext *ctx) \ { \ - CHK_SV; \ + CHK_SV(ctx); \ if (unlikely(!ctx->tm_enabled)) { \ gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ return; \ diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc index cfb27bd020404..39dde55e16f0c 100644 --- a/target/ppc/translate/fp-impl.c.inc +++ b/target/ppc/translate/fp-impl.c.inc @@ -854,7 +854,7 @@ static void gen_lfdepx(DisasContext *ctx) { TCGv EA; TCGv_i64 t0; - CHK_SV; + CHK_SV(ctx); if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); return; @@ -1011,7 +1011,7 @@ static void gen_stfdepx(DisasContext *ctx) { TCGv EA; TCGv_i64 t0; - CHK_SV; + CHK_SV(ctx); if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); return; diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc b/target/ppc/translate/storage-ctrl-impl.c.inc index 38b11ff956320..83f60c9166995 100644 --- a/target/ppc/translate/storage-ctrl-impl.c.inc +++ b/target/ppc/translate/storage-ctrl-impl.c.inc @@ -24,12 +24,14 @@ static bool do_slbie(DisasContext *ctx, arg_X_rb *a) { REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS(ctx, SLBI); REQUIRE_INSNS_FLAGS2(ctx, ISA300); #if defined(CONFIG_USER_ONLY) - GEN_PRIV2(true); + GEN_PRIV(ctx, true); #else - + CHK_SV(ctx, true); + #if defined(TARGET_PPC64) gen_helper_slbie(cpu_env, cpu_gpr[a->rb]); #else @@ -45,8 +47,9 @@ static bool do_slbieg(DisasContext *ctx, arg_X_tb *a) REQUIRE_INSNS_FLAGS2(ctx, ISA300); #if defined(CONFIG_USER_ONLY) - GEN_PRIV2(true); + GEN_PRIV(ctx, true); #else + CHK_SV(ctx, true); #if defined(TARGET_PPC64) gen_helper_slbieg(cpu_env, cpu_gpr[a->rb]); @@ -60,11 +63,13 @@ static bool do_slbieg(DisasContext *ctx, arg_X_tb *a) static bool do_slbia(DisasContext *ctx, arg_X_ih *a) { REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS(ctx, SLBI); REQUIRE_INSNS_FLAGS2(ctx, ISA300); #if defined(CONFIG_USER_ONLY) - GEN_PRIV2(true); + GEN_PRIV(ctx, true); #else + CHK_SV(ctx, true); #if defined(TARGET_PPC64) gen_helper_slbia(cpu_env, tcg_constant_i32(a->ih)); @@ -81,8 +86,9 @@ static bool do_slbiag(DisasContext *ctx, arg_X_rs_l *a) REQUIRE_INSNS_FLAGS2(ctx, ISA300); #if defined(CONFIG_USER_ONLY) - GEN_PRIV2(true); + GEN_PRIV(ctx, true); #else + CHK_SV(ctx, true); #if defined(TARGET_PPC64) gen_helper_SLBIAG(cpu_env, cpu_gpr[a->rs], tcg_constant_i32(a->l)); @@ -96,11 +102,13 @@ static bool do_slbiag(DisasContext *ctx, arg_X_rs_l *a) static bool do_slbmte(DisasContext *ctx, arg_X_tb *a) { REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS(ctx, SEGMENT_64B); REQUIRE_INSNS_FLAGS2(ctx, ISA300); #if defined(CONFIG_USER_ONLY) - GEN_PRIV2(true); + GEN_PRIV(ctx, true); #else + CHK_SV(ctx, true); #if defined(TARGET_PPC64) gen_helper_store_slb(cpu_env, cpu_gpr[a->rb], cpu_gpr[a->rt]); @@ -114,11 +122,13 @@ static bool do_slbmte(DisasContext *ctx, arg_X_tb *a) static bool do_slbmfev(DisasContext *ctx, arg_X_tb *a) { REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS(ctx, SEGMENT_64B); REQUIRE_INSNS_FLAGS2(ctx, ISA300); #if defined(CONFIG_USER_ONLY) - GEN_PRIV2(true); + GEN_PRIV(ctx, true); #else + CHK_SV(ctx, true); #if defined(TARGET_PPC64) gen_helper_load_slb_vsid(cpu_gpr[a->rt], cpu_env, @@ -133,11 +143,13 @@ static bool do_slbmfev(DisasContext *ctx, arg_X_tb *a) static bool do_slbmfee(DisasContext *ctx, arg_X_tb *a) { REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS(ctx, SEGMENT_64B); REQUIRE_INSNS_FLAGS2(ctx, ISA300); #if defined(CONFIG_USER_ONLY) - GEN_PRIV2(true); + GEN_PRIV(ctx, true); #else + CHK_SV(ctx, true); #if defined(TARGET_PPC64) gen_helper_load_slb_esid(cpu_gpr[a->rt],cpu_env, cpu_gpr[a->rb]); @@ -151,6 +163,7 @@ static bool do_slbmfee(DisasContext *ctx, arg_X_tb *a) static bool do_slbfee(DisasContext *ctx, arg_X_tb *a) { REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS(ctx, SEGMENT_64B); REQUIRE_INSNS_FLAGS2(ctx, ISA300); #if defined(CONFIG_USER_ONLY) @@ -186,8 +199,9 @@ static bool do_slbsync(DisasContext *ctx) { REQUIRE_64BIT(ctx); REQUIRE_INSNS_FLAGS2(ctx, ISA300); + #if defined(CONFIG_USER_ONLY) - GEN_PRIV2(true); + GEN_PRIV(ctx, true); #else #if defined(TARGET_PPC64) @@ -247,7 +261,7 @@ static bool trans_SLBSYNC(DisasContext *ctx, arg_SLBSYNC *a) static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local) { #if defined(CONFIG_USER_ONLY) - GEN_PRIV2(true); + GEN_PRIV(ctx, true); #else TCGv_i32 t1; int rb, ric; @@ -264,14 +278,14 @@ static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local) if (ctx->pr) { /* tlbie[l] is privileged... */ - GEN_PRIV2(true); + GEN_PRIV(ctx, true); } else if (!ctx->hv) { if ((!prs && ctx->hr) || (!local && !ctx->gtse)) { /* * ... except when PRS=0 and HR=1, or when GTSE=0 for tlbie, * making it hypervisor privileged. */ - GEN_PRIV2(true); + GEN_PRIV(ctx, true); } } From eb9712b484fa51d36ab92def5d19a0990506f25c Mon Sep 17 00:00:00 2001 From: Lucas Coutinho Date: Tue, 31 May 2022 14:43:25 -0300 Subject: [PATCH 11/13] target/ppc: Remove do_ functions --- target/ppc/translate/storage-ctrl-impl.c.inc | 65 +++----------------- 1 file changed, 10 insertions(+), 55 deletions(-) diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc b/target/ppc/translate/storage-ctrl-impl.c.inc index 83f60c9166995..ff0307ec2bf80 100644 --- a/target/ppc/translate/storage-ctrl-impl.c.inc +++ b/target/ppc/translate/storage-ctrl-impl.c.inc @@ -21,7 +21,7 @@ * Store Control Instructions */ -static bool do_slbie(DisasContext *ctx, arg_X_rb *a) +static bool trans_SLBIE(DisasContext *ctx, arg_SLBIE *a) { REQUIRE_64BIT(ctx); REQUIRE_INSNS_FLAGS(ctx, SLBI); @@ -41,7 +41,7 @@ static bool do_slbie(DisasContext *ctx, arg_X_rb *a) return true; } -static bool do_slbieg(DisasContext *ctx, arg_X_tb *a) +static bool trans_SLBIEG(DisasContext *ctx, arg_SLBIEG *a) { REQUIRE_64BIT(ctx); REQUIRE_INSNS_FLAGS2(ctx, ISA300); @@ -60,7 +60,7 @@ static bool do_slbieg(DisasContext *ctx, arg_X_tb *a) return true; } -static bool do_slbia(DisasContext *ctx, arg_X_ih *a) +static bool trans_SLBIA(DisasContext *ctx, arg_SLBIA *a) { REQUIRE_64BIT(ctx); REQUIRE_INSNS_FLAGS(ctx, SLBI); @@ -80,7 +80,7 @@ static bool do_slbia(DisasContext *ctx, arg_X_ih *a) return true; } -static bool do_slbiag(DisasContext *ctx, arg_X_rs_l *a) +static bool trans_SLBIAG(DisasContext *ctx, arg_SLBIAG *a) { REQUIRE_64BIT(ctx); REQUIRE_INSNS_FLAGS2(ctx, ISA300); @@ -99,7 +99,7 @@ static bool do_slbiag(DisasContext *ctx, arg_X_rs_l *a) return true; } -static bool do_slbmte(DisasContext *ctx, arg_X_tb *a) +static bool trans_SLBMTE(DisasContext *ctx, arg_SLBMTE *a) { REQUIRE_64BIT(ctx); REQUIRE_INSNS_FLAGS(ctx, SEGMENT_64B); @@ -119,7 +119,7 @@ static bool do_slbmte(DisasContext *ctx, arg_X_tb *a) return true; } -static bool do_slbmfev(DisasContext *ctx, arg_X_tb *a) +static bool trans_SLBMFEV(DisasContext *ctx, arg_SLBMFEV *a) { REQUIRE_64BIT(ctx); REQUIRE_INSNS_FLAGS(ctx, SEGMENT_64B); @@ -140,7 +140,7 @@ static bool do_slbmfev(DisasContext *ctx, arg_X_tb *a) return true; } -static bool do_slbmfee(DisasContext *ctx, arg_X_tb *a) +static bool trans_SLBMFEE(DisasContext *ctx, arg_SLBMFEE *a) { REQUIRE_64BIT(ctx); REQUIRE_INSNS_FLAGS(ctx, SEGMENT_64B); @@ -160,7 +160,7 @@ static bool do_slbmfee(DisasContext *ctx, arg_X_tb *a) return true; } -static bool do_slbfee(DisasContext *ctx, arg_X_tb *a) +static bool trans_SLBFEE(DisasContext *ctx, arg_SLBFEE *a) { REQUIRE_64BIT(ctx); REQUIRE_INSNS_FLAGS(ctx, SEGMENT_64B); @@ -195,8 +195,8 @@ static bool do_slbfee(DisasContext *ctx, arg_X_tb *a) return true; } -static bool do_slbsync(DisasContext *ctx) -{ +static bool trans_SLBSYNC(DisasContext *ctx, arg_SLBSYNC *a) +{ REQUIRE_64BIT(ctx); REQUIRE_INSNS_FLAGS2(ctx, ISA300); @@ -213,51 +213,6 @@ static bool do_slbsync(DisasContext *ctx) return true; } -static bool trans_SLBIE(DisasContext *ctx, arg_SLBIE *a) -{ - return do_slbie(ctx, a); -} - -static bool trans_SLBIEG(DisasContext *ctx, arg_SLBIEG *a) -{ - return do_slbieg(ctx, a); -} - -static bool trans_SLBIA(DisasContext *ctx, arg_SLBIA *a) -{ - return do_slbia(ctx, a); -} - -static bool trans_SLBIAG(DisasContext *ctx, arg_SLBIAG *a) -{ - return do_slbiag(ctx, a); -} - -static bool trans_SLBMTE(DisasContext *ctx, arg_SLBMTE *a) -{ - return do_slbmte(ctx, a); -} - -static bool trans_SLBMFEV(DisasContext *ctx, arg_SLBMFEV *a) -{ - return do_slbmfev(ctx, a); -} - -static bool trans_SLBMFEE(DisasContext *ctx, arg_SLBMFEE *a) -{ - return do_slbmfee(ctx, a); -} - -static bool trans_SLBFEE(DisasContext *ctx, arg_SLBFEE *a) -{ - return do_slbfee(ctx, a); -} - -static bool trans_SLBSYNC(DisasContext *ctx, arg_SLBSYNC *a) -{ - return do_slbsync(ctx); -} - static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local) { #if defined(CONFIG_USER_ONLY) From eadbe0da6549ca876b044e312a3e0ca915e34ef3 Mon Sep 17 00:00:00 2001 From: Lucas Coutinho Date: Tue, 31 May 2022 14:52:51 -0300 Subject: [PATCH 12/13] target/ppc: Fix comments --- target/ppc/mmu-hash64.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 874f49d779039..65ddeaa0bd06d 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -185,9 +185,9 @@ void helper_SLBIAG(CPUPPCState *env, target_ulong rs, uint32_t l) * can overwrite a valid SLB without flushing its lookaside information. * * It would be possible to keep the TLB in synch with the SLB by flushing - * when a valid entry is overwritten by slbmte, and therefore slbia would + * when a valid entry is overwritten by slbmte, and therefore slbiag would * not have to flush unless it evicts a valid SLB entry. However it is - * expected that slbmte is more common than slbia, and slbia is usually + * expected that slbmte is more common than slbiag, and slbiag is usually * going to evict valid SLB entries, so that tradeoff is unlikely to be a * good one. */ @@ -202,7 +202,7 @@ void helper_SLBIAG(CPUPPCState *env, target_ulong rs, uint32_t l) slb->esid &= ~SLB_ESID_V; } -} +} #endif static void __helper_slbie(CPUPPCState *env, target_ulong addr, From b1e0c02837c7d8f2a0241cc3cb9813fefbd2ebed Mon Sep 17 00:00:00 2001 From: Lucas Coutinho Date: Tue, 31 May 2022 16:21:49 -0300 Subject: [PATCH 13/13] target/ppc: Add missing CHK_SV --- target/ppc/translate/storage-ctrl-impl.c.inc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc b/target/ppc/translate/storage-ctrl-impl.c.inc index ff0307ec2bf80..6e9b20c963140 100644 --- a/target/ppc/translate/storage-ctrl-impl.c.inc +++ b/target/ppc/translate/storage-ctrl-impl.c.inc @@ -203,7 +203,8 @@ static bool trans_SLBSYNC(DisasContext *ctx, arg_SLBSYNC *a) #if defined(CONFIG_USER_ONLY) GEN_PRIV(ctx, true); #else - + CHK_SV(ctx, true); + #if defined(TARGET_PPC64) gen_check_tlb_flush(ctx, true); #else