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sakumisusakumisu
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update(cherryusb): update board config
Signed-off-by: sakumisu <[email protected]>
1 parent 07f20ac commit f5d59fe

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14 files changed

+226
-598
lines changed

14 files changed

+226
-598
lines changed

‎bsp/bouffalo_lab/bl61x/board/Kconfig

Lines changed: 1 addition & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -33,23 +33,17 @@ menuconfig BSP_USING_USB
3333
default n
3434
if BSP_USING_USB
3535
config BSP_USING_USB_DEVICE
36-
bool "Enable USB Device, default is msc ramdisk"
36+
bool "Enable USB Device"
3737
default n
3838
select RT_USING_CHERRYUSB
3939
select RT_CHERRYUSB_DEVICE
4040
select RT_CHERRYUSB_DEVICE_SPEED_HS
4141
select RT_CHERRYUSB_DEVICE_BL
42-
select RT_CHERRYUSB_DEVICE_MSC
43-
select RT_CHERRYUSB_DEVICE_TEMPLATE_MSC
4442
config BSP_USING_USB_HOST
4543
bool "Enable USB Host"
4644
default n
4745
select RT_USING_CACHE
4846
select RT_USING_CHERRYUSB
4947
select RT_CHERRYUSB_HOST
5048
select RT_CHERRYUSB_HOST_EHCI_BL
51-
select RT_CHERRYUSB_HOST_CDC_ACM
52-
select RT_CHERRYUSB_HOST_HID
53-
select RT_CHERRYUSB_HOST_MSC
54-
select RT_CHERRYUSB_HOST_CDC_RNDIS
5549
endif

‎bsp/bouffalo_lab/bl61x/board/usb_config.h

Lines changed: 77 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -6,11 +6,15 @@
66
#ifndef CHERRYUSB_CONFIG_H
77
#define CHERRYUSB_CONFIG_H
88

9-
#include <rtthread.h>
10-
119
/* ================ USB common Configuration ================ */
1210

11+
#ifdef __RTTHREAD__
12+
#include <rtthread.h>
13+
1314
#define CONFIG_USB_PRINTF(...) rt_kprintf(__VA_ARGS__)
15+
#else
16+
#define CONFIG_USB_PRINTF(...) printf(__VA_ARGS__)
17+
#endif
1418

1519
#ifndef CONFIG_USB_DBG_LEVEL
1620
#define CONFIG_USB_DBG_LEVEL USB_DBG_INFO
@@ -19,14 +23,23 @@
1923
/* Enable print with color */
2024
#define CONFIG_USB_PRINTF_COLOR_ENABLE
2125

22-
/* data align size when use dma */
23-
#ifndef CONFIG_USB_ALIGN_SIZE
26+
#define CONFIG_USB_DCACHE_ENABLE
27+
28+
/* data align size when use dma or use dcache */
29+
#ifdef CONFIG_USB_DCACHE_ENABLE
30+
#define CONFIG_USB_ALIGN_SIZE 32 // 32 or 64
31+
#else
2432
#define CONFIG_USB_ALIGN_SIZE 4
2533
#endif
2634

2735
/* attribute data into no cache ram */
2836
#define USB_NOCACHE_RAM_SECTION __attribute__((section(".noncacheable")))
2937

38+
/* use usb_memcpy default for high performance but cost more flash memory.
39+
* And, arm libc has a bug that memcpy() may cause data misalignment when the size is not a multiple of 4.
40+
*/
41+
// #define CONFIG_USB_MEMCPY_DISABLE
42+
3043
/* ================= USB Device Stack Configuration ================ */
3144

3245
/* Ep0 in and out transfer buffer */
@@ -48,6 +61,20 @@
4861
/* Enable test mode */
4962
// #define CONFIG_USBDEV_TEST_MODE
5063

64+
/* enable advance desc register api */
65+
#define CONFIG_USBDEV_ADVANCE_DESC
66+
67+
/* move ep0 setup handler from isr to thread */
68+
// #define CONFIG_USBDEV_EP0_THREAD
69+
70+
#ifndef CONFIG_USBDEV_EP0_PRIO
71+
#define CONFIG_USBDEV_EP0_PRIO 4
72+
#endif
73+
74+
#ifndef CONFIG_USBDEV_EP0_STACKSIZE
75+
#define CONFIG_USBDEV_EP0_STACKSIZE 2048
76+
#endif
77+
5178
#ifndef CONFIG_USBDEV_MSC_MAX_LUN
5279
#define CONFIG_USBDEV_MSC_MAX_LUN 1
5380
#endif
@@ -82,6 +109,28 @@
82109
#define CONFIG_USBDEV_MSC_STACKSIZE 2048
83110
#endif
84111

112+
#ifndef CONFIG_USBDEV_MTP_MAX_BUFSIZE
113+
#define CONFIG_USBDEV_MTP_MAX_BUFSIZE 2048
114+
#endif
115+
116+
#ifndef CONFIG_USBDEV_MTP_MAX_OBJECTS
117+
#define CONFIG_USBDEV_MTP_MAX_OBJECTS 256
118+
#endif
119+
120+
#ifndef CONFIG_USBDEV_MTP_MAX_PATHNAME
121+
#define CONFIG_USBDEV_MTP_MAX_PATHNAME 256
122+
#endif
123+
124+
#define CONFIG_USBDEV_MTP_THREAD
125+
126+
#ifndef CONFIG_USBDEV_MTP_PRIO
127+
#define CONFIG_USBDEV_MTP_PRIO 4
128+
#endif
129+
130+
#ifndef CONFIG_USBDEV_MTP_STACKSIZE
131+
#define CONFIG_USBDEV_MTP_STACKSIZE 4096
132+
#endif
133+
85134
#ifndef CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE
86135
#define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156
87136
#endif
@@ -100,6 +149,7 @@
100149
#endif
101150

102151
#define CONFIG_USBDEV_RNDIS_USING_LWIP
152+
#define CONFIG_USBDEV_CDC_ECM_USING_LWIP
103153

104154
/* ================ USB HOST Stack Configuration ================== */
105155

@@ -210,6 +260,11 @@
210260
#define CONFIG_USBDEV_EP_NUM 5
211261
#endif
212262

263+
// #define CONFIG_USBDEV_SOF_ENABLE
264+
265+
/* When your chip hardware supports high-speed and wants to initialize it in high-speed mode, the relevant IP will configure the internal or external high-speed PHY according to CONFIG_USB_HS. */
266+
#define CONFIG_USB_HS
267+
213268
/* ---------------- FSDEV Configuration ---------------- */
214269
//#define CONFIG_USBDEV_FSDEV_PMA_ACCESS 2 // maybe 1 or 2, many chips may have a difference
215270

@@ -220,7 +275,7 @@
220275
// #define CONFIG_USB_DWC2_RXALL_FIFO_SIZE (1024 / 4)
221276
/* IN Endpoints Max packet Size / 4 */
222277
// #define CONFIG_USB_DWC2_TX0_FIFO_SIZE (64 / 4)
223-
// #define CONFIG_USB_DWC2_TX1_FIFO_SIZE (512 / 4)
278+
// #define CONFIG_USB_DWC2_TX1_FIFO_SIZE (1024 / 4)
224279
// #define CONFIG_USB_DWC2_TX2_FIFO_SIZE (64 / 4)
225280
// #define CONFIG_USB_DWC2_TX3_FIFO_SIZE (64 / 4)
226281
// #define CONFIG_USB_DWC2_TX4_FIFO_SIZE (0 / 4)
@@ -229,6 +284,8 @@
229284
// #define CONFIG_USB_DWC2_TX7_FIFO_SIZE (0 / 4)
230285
// #define CONFIG_USB_DWC2_TX8_FIFO_SIZE (0 / 4)
231286

287+
// #define CONFIG_USB_DWC2_DMA_ENABLE
288+
232289
/* ---------------- MUSB Configuration ---------------- */
233290
// #define CONFIG_USB_MUSB_SUNXI
234291

@@ -246,15 +303,19 @@
246303
#define CONFIG_USB_EHCI_HCCR_OFFSET (0x0)
247304
#define CONFIG_USB_EHCI_FRAME_LIST_SIZE 1024
248305
#define CONFIG_USB_EHCI_QH_NUM CONFIG_USBHOST_PIPE_NUM
249-
#define CONFIG_USB_EHCI_QTD_NUM 3
250-
#define CONFIG_USB_EHCI_ITD_NUM 20
306+
#define CONFIG_USB_EHCI_QTD_NUM (CONFIG_USB_EHCI_QH_NUM * 3)
307+
#define CONFIG_USB_EHCI_ITD_NUM 4
251308
#define CONFIG_USB_EHCI_HCOR_RESERVED_DISABLE
252309
// #define CONFIG_USB_EHCI_CONFIGFLAG
253310
// #define CONFIG_USB_EHCI_ISO
254311
// #define CONFIG_USB_EHCI_WITH_OHCI
312+
// #define CONFIG_USB_EHCI_DESC_DCACHE_ENABLE
255313

256314
/* ---------------- OHCI Configuration ---------------- */
257315
#define CONFIG_USB_OHCI_HCOR_OFFSET (0x0)
316+
#define CONFIG_USB_OHCI_ED_NUM CONFIG_USBHOST_PIPE_NUM
317+
#define CONFIG_USB_OHCI_TD_NUM 3
318+
// #define CONFIG_USB_OHCI_DESC_DCACHE_ENABLE
258319

259320
/* ---------------- XHCI Configuration ---------------- */
260321
#define CONFIG_USB_XHCI_HCCR_OFFSET (0x0)
@@ -268,9 +329,17 @@
268329
* (largest USB packet used / 4) + 1 for status information + 1 transfer complete +
269330
* 1 location each for Bulk/Control endpoint for handling NAK/NYET scenario
270331
*/
271-
// #define CONFIG_USB_DWC2_RX_FIFO_SIZE ((1012 - CONFIG_USB_DWC2_NPTX_FIFO_SIZE - CONFIG_USB_DWC2_PTX_FIFO_SIZE) / 4)
332+
// #define CONFIG_USB_DWC2_RX_FIFO_SIZE ((1012 - CONFIG_USB_DWC2_NPTX_FIFO_SIZE - CONFIG_USB_DWC2_PTX_FIFO_SIZE))
272333

273334
/* ---------------- MUSB Configuration ---------------- */
274335
// #define CONFIG_USB_MUSB_SUNXI
275336

337+
#ifndef usb_phyaddr2ramaddr
338+
#define usb_phyaddr2ramaddr(addr) (addr)
339+
#endif
340+
341+
#ifndef usb_ramaddr2phyaddr
342+
#define usb_ramaddr2phyaddr(addr) (addr)
343+
#endif
344+
276345
#endif

‎bsp/hpmicro/hpm6750evk2/board/Kconfig

Lines changed: 1 addition & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -361,25 +361,19 @@ menu "On-chip Peripheral Drivers"
361361
default n
362362
if BSP_USING_USB
363363
config BSP_USING_USB_DEVICE
364-
bool "Enable USB Device, default is msc ramdisk"
364+
bool "Enable USB Device"
365365
default n
366366
select RT_USING_CHERRYUSB
367367
select RT_CHERRYUSB_DEVICE
368368
select RT_CHERRYUSB_DEVICE_SPEED_HS
369369
select RT_CHERRYUSB_DEVICE_HPM
370-
select RT_CHERRYUSB_DEVICE_MSC
371-
select RT_CHERRYUSB_DEVICE_TEMPLATE_MSC
372370
config BSP_USING_USB_HOST
373371
bool "Enable USB Host"
374372
default n
375373
select RT_USING_CACHE
376374
select RT_USING_CHERRYUSB
377375
select RT_CHERRYUSB_HOST
378376
select RT_CHERRYUSB_HOST_EHCI_HPM
379-
select RT_CHERRYUSB_HOST_CDC_ACM
380-
select RT_CHERRYUSB_HOST_HID
381-
select RT_CHERRYUSB_HOST_MSC
382-
select RT_CHERRYUSB_HOST_CDC_RNDIS
383377
endif
384378

385379

‎bsp/hpmicro/hpm6750evk2/board/usb_config.h

Lines changed: 72 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -20,14 +20,23 @@
2020
/* Enable print with color */
2121
#define CONFIG_USB_PRINTF_COLOR_ENABLE
2222

23-
/* data align size when use dma */
24-
#ifndef CONFIG_USB_ALIGN_SIZE
23+
#define CONFIG_USB_DCACHE_ENABLE
24+
25+
/* data align size when use dma or use dcache */
26+
#ifdef CONFIG_USB_DCACHE_ENABLE
27+
#define CONFIG_USB_ALIGN_SIZE HPM_L1C_CACHELINE_SIZE // 32 or 64
28+
#else
2529
#define CONFIG_USB_ALIGN_SIZE 4
2630
#endif
2731

2832
/* attribute data into no cache ram */
2933
#define USB_NOCACHE_RAM_SECTION __attribute__((section(".noncacheable")))
3034

35+
/* use usb_memcpy default for high performance but cost more flash memory.
36+
* And, arm libc has a bug that memcpy() may cause data misalignment when the size is not a multiple of 4.
37+
*/
38+
// #define CONFIG_USB_MEMCPY_DISABLE
39+
3140
/* ================= USB Device Stack Configuration ================ */
3241

3342
/* Ep0 in and out transfer buffer */
@@ -49,6 +58,20 @@
4958
/* Enable test mode */
5059
// #define CONFIG_USBDEV_TEST_MODE
5160

61+
/* enable advance desc register api */
62+
#define CONFIG_USBDEV_ADVANCE_DESC
63+
64+
/* move ep0 setup handler from isr to thread */
65+
// #define CONFIG_USBDEV_EP0_THREAD
66+
67+
#ifndef CONFIG_USBDEV_EP0_PRIO
68+
#define CONFIG_USBDEV_EP0_PRIO 4
69+
#endif
70+
71+
#ifndef CONFIG_USBDEV_EP0_STACKSIZE
72+
#define CONFIG_USBDEV_EP0_STACKSIZE 2048
73+
#endif
74+
5275
#ifndef CONFIG_USBDEV_MSC_MAX_LUN
5376
#define CONFIG_USBDEV_MSC_MAX_LUN 1
5477
#endif
@@ -83,6 +106,28 @@
83106
#define CONFIG_USBDEV_MSC_STACKSIZE 2048
84107
#endif
85108

109+
#ifndef CONFIG_USBDEV_MTP_MAX_BUFSIZE
110+
#define CONFIG_USBDEV_MTP_MAX_BUFSIZE 2048
111+
#endif
112+
113+
#ifndef CONFIG_USBDEV_MTP_MAX_OBJECTS
114+
#define CONFIG_USBDEV_MTP_MAX_OBJECTS 256
115+
#endif
116+
117+
#ifndef CONFIG_USBDEV_MTP_MAX_PATHNAME
118+
#define CONFIG_USBDEV_MTP_MAX_PATHNAME 256
119+
#endif
120+
121+
#define CONFIG_USBDEV_MTP_THREAD
122+
123+
#ifndef CONFIG_USBDEV_MTP_PRIO
124+
#define CONFIG_USBDEV_MTP_PRIO 4
125+
#endif
126+
127+
#ifndef CONFIG_USBDEV_MTP_STACKSIZE
128+
#define CONFIG_USBDEV_MTP_STACKSIZE 4096
129+
#endif
130+
86131
#ifndef CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE
87132
#define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156
88133
#endif
@@ -101,6 +146,7 @@
101146
#endif
102147

103148
#define CONFIG_USBDEV_RNDIS_USING_LWIP
149+
#define CONFIG_USBDEV_CDC_ECM_USING_LWIP
104150

105151
/* ================ USB HOST Stack Configuration ================== */
106152

@@ -211,6 +257,11 @@
211257
#define CONFIG_USBDEV_EP_NUM USB_SOC_DCD_MAX_ENDPOINT_COUNT
212258
#endif
213259

260+
// #define CONFIG_USBDEV_SOF_ENABLE
261+
262+
/* When your chip hardware supports high-speed and wants to initialize it in high-speed mode, the relevant IP will configure the internal or external high-speed PHY according to CONFIG_USB_HS. */
263+
#define CONFIG_USB_HS
264+
214265
/* ---------------- FSDEV Configuration ---------------- */
215266
//#define CONFIG_USBDEV_FSDEV_PMA_ACCESS 2 // maybe 1 or 2, many chips may have a difference
216267

@@ -221,7 +272,7 @@
221272
// #define CONFIG_USB_DWC2_RXALL_FIFO_SIZE (1024 / 4)
222273
/* IN Endpoints Max packet Size / 4 */
223274
// #define CONFIG_USB_DWC2_TX0_FIFO_SIZE (64 / 4)
224-
// #define CONFIG_USB_DWC2_TX1_FIFO_SIZE (512 / 4)
275+
// #define CONFIG_USB_DWC2_TX1_FIFO_SIZE (1024 / 4)
225276
// #define CONFIG_USB_DWC2_TX2_FIFO_SIZE (64 / 4)
226277
// #define CONFIG_USB_DWC2_TX3_FIFO_SIZE (64 / 4)
227278
// #define CONFIG_USB_DWC2_TX4_FIFO_SIZE (0 / 4)
@@ -230,6 +281,8 @@
230281
// #define CONFIG_USB_DWC2_TX7_FIFO_SIZE (0 / 4)
231282
// #define CONFIG_USB_DWC2_TX8_FIFO_SIZE (0 / 4)
232283

284+
// #define CONFIG_USB_DWC2_DMA_ENABLE
285+
233286
/* ---------------- MUSB Configuration ---------------- */
234287
// #define CONFIG_USB_MUSB_SUNXI
235288

@@ -247,15 +300,19 @@
247300
#define CONFIG_USB_EHCI_HCCR_OFFSET (0x100)
248301
#define CONFIG_USB_EHCI_FRAME_LIST_SIZE 1024
249302
#define CONFIG_USB_EHCI_QH_NUM CONFIG_USBHOST_PIPE_NUM
250-
#define CONFIG_USB_EHCI_QTD_NUM 3
251-
#define CONFIG_USB_EHCI_ITD_NUM 20
303+
#define CONFIG_USB_EHCI_QTD_NUM (CONFIG_USB_EHCI_QH_NUM * 3)
304+
#define CONFIG_USB_EHCI_ITD_NUM 4
252305
// #define CONFIG_USB_EHCI_HCOR_RESERVED_DISABLE
253306
// #define CONFIG_USB_EHCI_CONFIGFLAG
254307
// #define CONFIG_USB_EHCI_ISO
255308
// #define CONFIG_USB_EHCI_WITH_OHCI
309+
// #define CONFIG_USB_EHCI_DESC_DCACHE_ENABLE
256310

257311
/* ---------------- OHCI Configuration ---------------- */
258312
#define CONFIG_USB_OHCI_HCOR_OFFSET (0x0)
313+
#define CONFIG_USB_OHCI_ED_NUM CONFIG_USBHOST_PIPE_NUM
314+
#define CONFIG_USB_OHCI_TD_NUM 3
315+
// #define CONFIG_USB_OHCI_DESC_DCACHE_ENABLE
259316

260317
/* ---------------- XHCI Configuration ---------------- */
261318
#define CONFIG_USB_XHCI_HCCR_OFFSET (0x0)
@@ -269,11 +326,19 @@
269326
* (largest USB packet used / 4) + 1 for status information + 1 transfer complete +
270327
* 1 location each for Bulk/Control endpoint for handling NAK/NYET scenario
271328
*/
272-
// #define CONFIG_USB_DWC2_RX_FIFO_SIZE ((1012 - CONFIG_USB_DWC2_NPTX_FIFO_SIZE - CONFIG_USB_DWC2_PTX_FIFO_SIZE) / 4)
329+
// #define CONFIG_USB_DWC2_RX_FIFO_SIZE ((1012 - CONFIG_USB_DWC2_NPTX_FIFO_SIZE - CONFIG_USB_DWC2_PTX_FIFO_SIZE))
273330

274331
/* ---------------- MUSB Configuration ---------------- */
275332
// #define CONFIG_USB_MUSB_SUNXI
276333

277-
#define CONFIG_USB_EHCI_HPMICRO (1)
334+
#ifndef usb_phyaddr2ramaddr
335+
#define usb_phyaddr2ramaddr(addr) (addr)
336+
#endif
337+
338+
#ifndef usb_ramaddr2phyaddr
339+
#define usb_ramaddr2phyaddr(addr) (addr)
340+
#endif
341+
342+
#define CONFIG_USB_EHCI_HPMICRO 1
278343

279344
#endif

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