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LegNeatoeddyb
LegNeato
authored and
eddyb
committed
Switch all crates to Rust 2024 edition.
1 parent b9d4176 commit cd97c5b

25 files changed

+1162
-976
lines changed

‎Cargo.toml

+1-1
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@ members = [
3131
[workspace.package]
3232
version = "0.9.0"
3333
authors = ["rust-gpu developers", "Embark <[email protected]>"]
34-
edition = "2021"
34+
edition = "2024"
3535
license = "MIT OR Apache-2.0"
3636
repository = "https://github.com/rust-gpu/rust-gpu"
3737

‎crates/rustc_codegen_spirv/Cargo.toml

+1-1
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@ description = "SPIR-V code generator backend for rustc"
44
documentation = "https://rust-gpu.github.io/rust-gpu/api/rustc_codegen_spirv/index.html"
55
version.workspace = true
66
authors.workspace = true
7-
edition = "2024"
7+
edition.workspace = true
88
license.workspace = true
99
repository.workspace = true
1010

‎crates/spirv-std/src/arch.rs

+119-101
Original file line numberDiff line numberDiff line change
@@ -87,18 +87,20 @@ pub unsafe fn vector_extract_dynamic<T: Scalar, const N: usize>(
8787
vector: impl Vector<T, N>,
8888
index: usize,
8989
) -> T {
90-
let mut result = T::default();
91-
92-
asm! {
93-
"%vector = OpLoad _ {vector}",
94-
"%element = OpVectorExtractDynamic _ %vector {index}",
95-
"OpStore {element} %element",
96-
vector = in(reg) &vector,
97-
index = in(reg) index,
98-
element = in(reg) &mut result
99-
}
90+
unsafe {
91+
let mut result = T::default();
10092

101-
result
93+
asm! {
94+
"%vector = OpLoad _ {vector}",
95+
"%element = OpVectorExtractDynamic _ %vector {index}",
96+
"OpStore {element} %element",
97+
vector = in(reg) &vector,
98+
index = in(reg) index,
99+
element = in(reg) &mut result
100+
}
101+
102+
result
103+
}
102104
}
103105

104106
/// Make a copy of a vector, with a single, variably selected,
@@ -115,20 +117,22 @@ pub unsafe fn vector_insert_dynamic<T: Scalar, V: Vector<T, N>, const N: usize>(
115117
index: usize,
116118
element: T,
117119
) -> V {
118-
let mut result = V::default();
119-
120-
asm! {
121-
"%vector = OpLoad _ {vector}",
122-
"%element = OpLoad _ {element}",
123-
"%new_vector = OpVectorInsertDynamic _ %vector %element {index}",
124-
"OpStore {result} %new_vector",
125-
vector = in(reg) &vector,
126-
index = in(reg) index,
127-
element = in(reg) &element,
128-
result = in(reg) &mut result,
129-
}
120+
unsafe {
121+
let mut result = V::default();
130122

131-
result
123+
asm! {
124+
"%vector = OpLoad _ {vector}",
125+
"%element = OpLoad _ {element}",
126+
"%new_vector = OpVectorInsertDynamic _ %vector %element {index}",
127+
"OpStore {result} %new_vector",
128+
vector = in(reg) &vector,
129+
index = in(reg) index,
130+
element = in(reg) &element,
131+
result = in(reg) &mut result,
132+
}
133+
134+
result
135+
}
132136
}
133137

134138
/// Fragment-shader discard. Equivalvent to `discard()` from GLSL
@@ -155,17 +159,19 @@ pub fn kill() -> ! {
155159
#[spirv_std_macros::gpu_only]
156160
#[doc(alias = "OpReadClockKHR")]
157161
pub unsafe fn read_clock_khr<const SCOPE: u32>() -> u64 {
158-
let mut result: u64;
159-
160-
asm! {
161-
"%uint = OpTypeInt 32 0",
162-
"%scope = OpConstant %uint {scope}",
163-
"{result} = OpReadClockKHR typeof*{result} %scope",
164-
result = out(reg) result,
165-
scope = const SCOPE,
166-
};
162+
unsafe {
163+
let mut result: u64;
167164

168-
result
165+
asm! {
166+
"%uint = OpTypeInt 32 0",
167+
"%scope = OpConstant %uint {scope}",
168+
"{result} = OpReadClockKHR typeof*{result} %scope",
169+
result = out(reg) result,
170+
scope = const SCOPE,
171+
};
172+
173+
result
174+
}
169175
}
170176

171177
/// Like `read_clock_khr` but returns a vector to avoid requiring the `Int64`
@@ -179,35 +185,39 @@ pub unsafe fn read_clock_khr<const SCOPE: u32>() -> u64 {
179185
#[spirv_std_macros::gpu_only]
180186
#[doc(alias = "OpReadClockKHR")]
181187
pub unsafe fn read_clock_uvec2_khr<V: Vector<u32, 2>, const SCOPE: u32>() -> V {
182-
let mut result = V::default();
188+
unsafe {
189+
let mut result = V::default();
183190

184-
asm! {
185-
"%uint = OpTypeInt 32 0",
186-
"%scope = OpConstant %uint {scope}",
187-
"%result = OpReadClockKHR typeof*{result} %scope",
188-
"OpStore {result} %result",
189-
result = in(reg) &mut result,
190-
scope = const SCOPE,
191-
};
191+
asm! {
192+
"%uint = OpTypeInt 32 0",
193+
"%scope = OpConstant %uint {scope}",
194+
"%result = OpReadClockKHR typeof*{result} %scope",
195+
"OpStore {result} %result",
196+
result = in(reg) &mut result,
197+
scope = const SCOPE,
198+
};
192199

193-
result
200+
result
201+
}
194202
}
195203

196204
#[cfg(target_arch = "spirv")]
197205
unsafe fn call_glsl_op_with_ints<T: Integer, const OP: u32>(a: T, b: T) -> T {
198-
let mut result = T::default();
199-
asm!(
200-
"%glsl = OpExtInstImport \"GLSL.std.450\"",
201-
"%a = OpLoad _ {a}",
202-
"%b = OpLoad _ {b}",
203-
"%result = OpExtInst typeof*{result} %glsl {op} %a %b",
204-
"OpStore {result} %result",
205-
a = in(reg) &a,
206-
b = in(reg) &b,
207-
result = in(reg) &mut result,
208-
op = const OP
209-
);
210-
result
206+
unsafe {
207+
let mut result = T::default();
208+
asm!(
209+
"%glsl = OpExtInstImport \"GLSL.std.450\"",
210+
"%a = OpLoad _ {a}",
211+
"%b = OpLoad _ {b}",
212+
"%result = OpExtInst typeof*{result} %glsl {op} %a %b",
213+
"OpStore {result} %result",
214+
a = in(reg) &a,
215+
b = in(reg) &b,
216+
result = in(reg) &mut result,
217+
op = const OP
218+
);
219+
result
220+
}
211221
}
212222

213223
/// Compute the minimum of two unsigned integers via a GLSL extended instruction.
@@ -254,83 +264,91 @@ pub trait IndexUnchecked<T> {
254264
impl<T> IndexUnchecked<T> for [T] {
255265
#[cfg(target_arch = "spirv")]
256266
unsafe fn index_unchecked(&self, index: usize) -> &T {
257-
// FIXME(eddyb) `let mut result = T::default()` uses (for `asm!`), with this.
258-
let mut result_slot = core::mem::MaybeUninit::uninit();
259-
asm! {
260-
"%slice_ptr = OpLoad _ {slice_ptr_ptr}",
261-
"%data_ptr = OpCompositeExtract _ %slice_ptr 0",
262-
"%result = OpAccessChain _ %data_ptr {index}",
263-
"OpStore {result_slot} %result",
264-
slice_ptr_ptr = in(reg) &self,
265-
index = in(reg) index,
266-
result_slot = in(reg) result_slot.as_mut_ptr(),
267+
unsafe {
268+
// FIXME(eddyb) `let mut result = T::default()` uses (for `asm!`), with this.
269+
let mut result_slot = core::mem::MaybeUninit::uninit();
270+
asm! {
271+
"%slice_ptr = OpLoad _ {slice_ptr_ptr}",
272+
"%data_ptr = OpCompositeExtract _ %slice_ptr 0",
273+
"%result = OpAccessChain _ %data_ptr {index}",
274+
"OpStore {result_slot} %result",
275+
slice_ptr_ptr = in(reg) &self,
276+
index = in(reg) index,
277+
result_slot = in(reg) result_slot.as_mut_ptr(),
278+
}
279+
result_slot.assume_init()
267280
}
268-
result_slot.assume_init()
269281
}
270282

271283
#[cfg(not(target_arch = "spirv"))]
272284
unsafe fn index_unchecked(&self, index: usize) -> &T {
273-
self.get_unchecked(index)
285+
unsafe { self.get_unchecked(index) }
274286
}
275287

276288
#[cfg(target_arch = "spirv")]
277289
unsafe fn index_unchecked_mut(&mut self, index: usize) -> &mut T {
278-
// FIXME(eddyb) `let mut result = T::default()` uses (for `asm!`), with this.
279-
let mut result_slot = core::mem::MaybeUninit::uninit();
280-
asm! {
281-
"%slice_ptr = OpLoad _ {slice_ptr_ptr}",
282-
"%data_ptr = OpCompositeExtract _ %slice_ptr 0",
283-
"%result = OpAccessChain _ %data_ptr {index}",
284-
"OpStore {result_slot} %result",
285-
slice_ptr_ptr = in(reg) &self,
286-
index = in(reg) index,
287-
result_slot = in(reg) result_slot.as_mut_ptr(),
290+
unsafe {
291+
// FIXME(eddyb) `let mut result = T::default()` uses (for `asm!`), with this.
292+
let mut result_slot = core::mem::MaybeUninit::uninit();
293+
asm! {
294+
"%slice_ptr = OpLoad _ {slice_ptr_ptr}",
295+
"%data_ptr = OpCompositeExtract _ %slice_ptr 0",
296+
"%result = OpAccessChain _ %data_ptr {index}",
297+
"OpStore {result_slot} %result",
298+
slice_ptr_ptr = in(reg) &self,
299+
index = in(reg) index,
300+
result_slot = in(reg) result_slot.as_mut_ptr(),
301+
}
302+
result_slot.assume_init()
288303
}
289-
result_slot.assume_init()
290304
}
291305

292306
#[cfg(not(target_arch = "spirv"))]
293307
unsafe fn index_unchecked_mut(&mut self, index: usize) -> &mut T {
294-
self.get_unchecked_mut(index)
308+
unsafe { self.get_unchecked_mut(index) }
295309
}
296310
}
297311

298312
impl<T, const N: usize> IndexUnchecked<T> for [T; N] {
299313
#[cfg(target_arch = "spirv")]
300314
unsafe fn index_unchecked(&self, index: usize) -> &T {
301-
// FIXME(eddyb) `let mut result = T::default()` uses (for `asm!`), with this.
302-
let mut result_slot = core::mem::MaybeUninit::uninit();
303-
asm! {
304-
"%result = OpAccessChain _ {array_ptr} {index}",
305-
"OpStore {result_slot} %result",
306-
array_ptr = in(reg) self,
307-
index = in(reg) index,
308-
result_slot = in(reg) result_slot.as_mut_ptr(),
315+
unsafe {
316+
// FIXME(eddyb) `let mut result = T::default()` uses (for `asm!`), with this.
317+
let mut result_slot = core::mem::MaybeUninit::uninit();
318+
asm! {
319+
"%result = OpAccessChain _ {array_ptr} {index}",
320+
"OpStore {result_slot} %result",
321+
array_ptr = in(reg) self,
322+
index = in(reg) index,
323+
result_slot = in(reg) result_slot.as_mut_ptr(),
324+
}
325+
result_slot.assume_init()
309326
}
310-
result_slot.assume_init()
311327
}
312328

313329
#[cfg(not(target_arch = "spirv"))]
314330
unsafe fn index_unchecked(&self, index: usize) -> &T {
315-
self.get_unchecked(index)
331+
unsafe { self.get_unchecked(index) }
316332
}
317333

318334
#[cfg(target_arch = "spirv")]
319335
unsafe fn index_unchecked_mut(&mut self, index: usize) -> &mut T {
320-
// FIXME(eddyb) `let mut result = T::default()` uses (for `asm!`), with this.
321-
let mut result_slot = core::mem::MaybeUninit::uninit();
322-
asm! {
323-
"%result = OpAccessChain _ {array_ptr} {index}",
324-
"OpStore {result_slot} %result",
325-
array_ptr = in(reg) self,
326-
index = in(reg) index,
327-
result_slot = in(reg) result_slot.as_mut_ptr(),
336+
unsafe {
337+
// FIXME(eddyb) `let mut result = T::default()` uses (for `asm!`), with this.
338+
let mut result_slot = core::mem::MaybeUninit::uninit();
339+
asm! {
340+
"%result = OpAccessChain _ {array_ptr} {index}",
341+
"OpStore {result_slot} %result",
342+
array_ptr = in(reg) self,
343+
index = in(reg) index,
344+
result_slot = in(reg) result_slot.as_mut_ptr(),
345+
}
346+
result_slot.assume_init()
328347
}
329-
result_slot.assume_init()
330348
}
331349

332350
#[cfg(not(target_arch = "spirv"))]
333351
unsafe fn index_unchecked_mut(&mut self, index: usize) -> &mut T {
334-
self.get_unchecked_mut(index)
352+
unsafe { self.get_unchecked_mut(index) }
335353
}
336354
}

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