Accessing signals defined inside elaborate() without prepending with self. in simulation

[goekce]

Is it possible to access the signal s without saving it to the component using self.s? (similar to hierarchical access in HDLs)

from amaranth import *
from amaranth.lib.wiring import Component, In, Out


class C(Component):
    o: Out(1)

    def elaborate(self, platform):
        m = Module()
        s = Signal()  # self.s = s = Signal() would work
        m.d.sync += self.o.eq(s)
        return m


from amaranth.sim import Period, Simulator

dut = C()


async def bench(ctx):
    for _ in range(2):
        await ctx.tick()
        print(ctx.get(dut.s))


sim = Simulator(dut)
sim.add_clock(Period())
sim.add_testbench(bench)
sim.run()

[whitequark]

If you need to introspect the object state during simulation, I will advise creating and exposing the signals you need to access in __init__ rather than elaborate. They effectively become a part of the component's interface, even if this interface is only used between the component and its tests. This is a bit different from how most software testing goes but is unavoidable due to Amaranth's approach for constructing designs.

[goekce]

In other words, signals that I want to have visibility of should be attributes of the component like this:

from amaranth import *
from amaranth.lib.wiring import Component, In, Out


class C(Component):
    o: Out(1)
    s = Signal()

    def elaborate(self, platform):
        m = Module()
        m.d.sync += self.o.eq(self.s)
        return m


from amaranth.sim import Period, Simulator

dut = C()


async def bench(ctx):
    for _ in range(2):
        print(ctx.get(dut.s))
        await ctx.tick()


sim = Simulator(dut)
sim.add_clock(Period())
sim.add_testbench(bench)
sim.run()

Variable annotations are useful not only for the signature (input and outputs) but also for test signals. After reading the interface documentation I had the assumption that the variable annotations are only for the signature.

[whitequark]

No, that's not what I'm talking about. It should be like:

class C(Component):
    o: Out(1)

    def __init__(self):
        self.s = Signal()
        super().__init__()

    def elaborate(self, platform):
        m = Module()
        m.d.sync += self.o.eq(self.s)
        return m

The code you wrote will break if you instantiate the component multiple times, so you shouldn't use it.

[goekce]

Thanks, so interface documentation is indeed correct that I should use the variable annotations only for the port (In, Out, etc) signals.