transcript

# Errors: 12, Warnings: 0
# Errors: 0, Warnings: 0
# Compile of sharp_arith.vhd was successful.
# Errors: 0, Warnings: 0
# Compile of sharp_control.vhd was successful.
# Errors: 0, Warnings: 0
# Compile of sharp_linemem.vhd was successful.
# Errors: 0, Warnings: 0
# Compile of sharp_slice.vhd was successful.
# Errors: 0, Warnings: 0
# Compile of sim_sharp.vhd was successful.
# Errors: 0, Warnings: 2
# Compile of sim_sharp_self-checking.vhd was successful.
# Errors: 0, Warnings: 0
# Compile of sharp.vhd was successful.
# Compile of sharp_arith.vhd was successful.
# Compile of sharp_control.vhd was successful.
# Compile of sharp_linemem.vhd was successful.
# Compile of sharp_slice.vhd was successful.
# Compile of sim_sharp.vhd was successful with warnings.
# Compile of sim_sharp_self-checking.vhd was successful with warnings.
# Compile of sharp.vhd was successful.
# 7 compiles, 0 failed with no errors.
# Compile of sim_sharp.vhd was successful with warnings.
# Errors: 0, Warnings: 0
# Compile of sharp_arith.vhd was successful.
# Errors: 0, Warnings: 0
# Compile of sharp_control.vhd was successful.
# Errors: 0, Warnings: 0
# Compile of sharp_linemem.vhd was successful.
# Errors: 0, Warnings: 0
# Compile of sharp_slice.vhd was successful.
# Errors: 0, Warnings: 0
# Compile of sim_sharp.vhd was successful.
# Errors: 0, Warnings: 2
# Compile of sim_sharp_self-checking.vhd was successful.
# Errors: 0, Warnings: 0
# Compile of sharp.vhd was successful.
# Compile of sharp_arith.vhd was successful.
# Compile of sharp_control.vhd was successful.
# Compile of sharp_linemem.vhd was successful.
# Compile of sharp_slice.vhd was successful.
# Compile of sim_sharp.vhd was successful with warnings.
# Compile of sim_sharp_self-checking.vhd was successful with warnings.
# Compile of sharp.vhd was successful.
# 7 compiles, 0 failed with no errors.
vsim work.sim_sharp(sim)
# vsim work.sim_sharp(sim) 
# Start time: 15:12:31 on Jan 22,2025
# ** Note: (vsim-3812) Design is being optimized...
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading ieee.std_logic_textio(body)
# Loading work.sim_sharp(sim)#1
# Loading work.sharp_slice(behave)#1
add wave -position insertpoint  \
sim:/sim_sharp/b_in \
sim:/sim_sharp/de_in \
sim:/sim_sharp/g_in \
sim:/sim_sharp/hs_in \
sim:/sim_sharp/r_in \
sim:/sim_sharp/vs_in
run
# ** Fatal: (vsim-7) Failed to open VHDL file "Lindau_Harbour_720p.ppm" in rb mode.
# No such file or directory. (errno = ENOENT)
#    Time: 0 ns  Iteration: 0  Process: /sim_sharp/stimuli_process File: C:/Users/jonel/OneDrive/Desktop/VHDL Projects/FPGA-FIR-Filter-master/FPGA-FIR-Filter-master/Verification/sim_sharp_self-checking.vhd
# Fatal error in Process stimuli_process at C:/Users/jonel/OneDrive/Desktop/VHDL Projects/FPGA-FIR-Filter-master/FPGA-FIR-Filter-master/Verification/sim_sharp_self-checking.vhd line 90
# 
# HDL call sequence:
# Stopped at C:/Users/jonel/OneDrive/Desktop/VHDL Projects/FPGA-FIR-Filter-master/FPGA-FIR-Filter-master/Verification/sim_sharp_self-checking.vhd 90 Process stimuli_process
# 
run
# Cannot continue because of fatal error.
# HDL call sequence:
# Stopped at C:/Users/jonel/OneDrive/Desktop/VHDL Projects/FPGA-FIR-Filter-master/FPGA-FIR-Filter-master/Verification/sim_sharp_self-checking.vhd 90 Process stimuli_process
# 
run
# Cannot continue because of fatal error.
# HDL call sequence:
# Stopped at C:/Users/jonel/OneDrive/Desktop/VHDL Projects/FPGA-FIR-Filter-master/FPGA-FIR-Filter-master/Verification/sim_sharp_self-checking.vhd 90 Process stimuli_process
# 
quit -sim
# End time: 15:15:20 on Jan 22,2025, Elapsed time: 0:02:49
# Errors: 1, Warnings: 10
# Errors: 0, Warnings: 0
# Compile of sharp_arith.vhd was successful.
# Errors: 0, Warnings: 0
# Compile of sharp_control.vhd was successful.
# Errors: 0, Warnings: 0
# Compile of sharp_linemem.vhd was successful.
# Errors: 0, Warnings: 0
# Compile of sharp_slice.vhd was successful.
# Errors: 0, Warnings: 2
# Compile of sim_sharp.vhd was successful.
# Errors: 0, Warnings: 0
# Compile of sharp.vhd was successful.
# Compile of sharp_arith.vhd was successful.
# Compile of sharp_control.vhd was successful.
# Compile of sharp_linemem.vhd was successful.
# Compile of sharp_slice.vhd was successful.
# Compile of sim_sharp.vhd was successful.
# Compile of sharp.vhd was successful.
# 6 compiles, 0 failed with no errors.
vsim work.sim_sharp(sim)
# vsim work.sim_sharp(sim) 
# Start time: 15:16:15 on Jan 22,2025
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading ieee.std_logic_textio(body)
# Loading work.sim_sharp(sim)#1
# Loading work.sharp_slice(behave)#1
add wave -position insertpoint  \
sim:/sim_sharp/b_in \
sim:/sim_sharp/de_in \
sim:/sim_sharp/g_in \
sim:/sim_sharp/hs_in \
sim:/sim_sharp/r_in
run
run -continue
run -continue
run -continue
run
run
run
run
run
run
run -all
# Break key hit
# Simulation stop requested.
quit -sim
# End time: 15:21:58 on Jan 22,2025, Elapsed time: 0:05:43
# Errors: 0, Warnings: 4
# Errors: 0, Warnings: 0
# Compile of sharp.vhd was successful.
# Errors: 0, Warnings: 0
# Compile of sharp_linemem.vhd was successful.
# Errors: 0, Warnings: 0
# Compile of sharp_arith.vhd was successful.
# Errors: 0, Warnings: 0
# Compile of sharp_slice.vhd was successful.
# Errors: 0, Warnings: 0
# Compile of sharp_control.vhd was successful.
# Errors: 0, Warnings: 0
# Compile of sim_sharp.vhd was successful.
vsim work.sim_sharp
# vsim work.sim_sharp 
# Start time: 15:23:12 on Jan 22,2025
# ** Note: (vsim-8009) Loading existing optimized design _opt
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading ieee.std_logic_textio(body)
# Loading work.sim_sharp(sim)#1
# Loading work.sharp_slice(behave)#1
add wave -position insertpoint sim:/sim_sharp/*
run -all
# ** Failure: Simulation completed
#    Time: 8902120 ns  Iteration: 0  Process: /sim_sharp/stimuli_process File: C:/Users/jonel/OneDrive/Desktop/VHDL Projects/FPGA-FIR-Filter-master/FPGA-FIR-Filter-master/Verification/sim_sharp.vhd
# Break in Process stimuli_process at C:/Users/jonel/OneDrive/Desktop/VHDL Projects/FPGA-FIR-Filter-master/FPGA-FIR-Filter-master/Verification/sim_sharp.vhd line 164