-
Notifications
You must be signed in to change notification settings - Fork 2
/
Copy pathcom.github.reds.LogisimEvolution.metainfo.xml
205 lines (205 loc) · 11.1 KB
/
com.github.reds.LogisimEvolution.metainfo.xml
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
<?xml version="1.0" encoding="UTF-8"?>
<component type="desktop-application">
<id>com.github.reds.LogisimEvolution</id>
<metadata_license>CC0-1.0</metadata_license>
<project_license>GPL-3.0</project_license>
<name>Logisim-evolution</name>
<summary>Digital logic designer and simulator</summary>
<developer_name>Logisim-evolution developers</developer_name>
<url type="homepage">https://github.com/logisim-evolution/logisim-evolution</url>
<launchable type="desktop-id">com.github.reds.LogisimEvolution.desktop</launchable>
<description>
<p>Logisim-evolution is a completely free and open-source educational, cross-platform software for designing and simulating digital logic circuits.</p>
<p>Project highlights:</p>
<ul>
<li>easy to use circuit designer</li>
<li>logic circuit simulations</li>
<li>chronogram (to see the evolution of signals in your circuit)</li>
<li>electronic board integration - schematics can now be simulated on real hardware</li>
<li>VHDL components (components whose behavior is specified in VHDL!)</li>
<li>TCL/TK console (interfaces between the circuit and the user)</li>
<li>huge library of components (LEDs, TTLs, switches, SoCs)</li>
<li>Supports multiple languages</li>
<li>and more!</li>
</ul>
</description>
<screenshots>
<screenshot type="default">
<image>https://raw.githubusercontent.com/logisim-evolution/logisim-evolution/develop/docs/img/logisim-evolution-01.png</image>
<caption>Design view</caption>
</screenshot>
<screenshot>
<image>https://raw.githubusercontent.com/logisim-evolution/logisim-evolution/develop/docs/img/logisim-evolution-02.png</image>
<caption>Design view</caption>
</screenshot>
</screenshots>
<releases>
<release version="3.9.0" date="2024-08-15">
<description>
<ul>
<li>Updated Java requirement to Java 21.</li>
<li>Added an autosave feature along with preferences for it.</li>
<li>Added a new preference to allow the user to choose the action keys for many functions.</li>
<li>Changed RAM default output from error to undefined</li>
<li>Added support for scanning 7-segment display on FPGA-boards</li>
<li>Added first support for the openFpga toolchain for the ecp5 family</li>
<li>Note that this is experimental for the moment, so use it at your own risk.</li>
<li>Improved Chinese localization</li>
<li>Changed language code from cn to zh.</li>
<li>Chinese users (also including those who use other forks of Logisim that are using cn language code) will be required to manually modify language settings.</li>
<li>Fixed select port positioning on Multiplexer to be more consistent in some cases</li>
<li>Fixed appearance of LSe desktop icon</li>
<li>Update controlled buffer behavior to pass U and E inputs while enabled</li>
<li>Introduced user-defined color for components.</li>
<li>Made component icons more uniform.</li>
<li>Added architecture designation to macOS build.</li>
<li>Fixed Karnaugh map color index bug.</li>
<li>Attribute sheet now honors application color theme.</li>
<li>Attribute sheet now displays HEX value of color properties.</li>
<li>Added TTL 7487: 4-bit True/complement, zero/one elements</li>
<li>Fixed Wrong HDL generation bug in the PortIO component and added the single bit version.</li>
<li>Added TTL 74151: 8-line to 1 line data selector</li>
<li>Added TTL 74153: dual 4-line to 1 line data selector</li>
<li>Added TTL 74181: arithmetic logic unit</li>
<li>Added TTL 74182: look-ahead carry generator</li>
<li>Added TTL 74299: 8-bit universal shift register with three-state outputs</li>
<li>Added TTL 74381: arithmetic logic unit</li>
<li>Added TTL 74541: Octal buffers with three-state outputs</li>
<li>Added TTL 74670: 4-by-4 register file with three-state outputs</li>
<li>Added 16 bit floating point support for floating point arithmetic</li>
<li>Fixed the problem of keys getting assigned to focusing on the cell of the table in "properties" section along with its actual intent</li>
</ul>
</description>
</release>
<release version="3.8.0" date="2022-10-02">
<description>
<ul>
<li>Added reset value attribute to input pins</li>
<li>Fixed boolean algebra minimal form bug</li>
<li>Fixed random fill Rom bug</li>
<li>Added TTL 74164, 74192 and 74193.</li>
<li>Fixed off grid components bug that could lead to OutOfMemory error.</li>
<li>Removed autolabler for tunnels, such that all get the same label in case of renaming.</li>
<li>Fixed bug preventing TTL 7442, 7443 and 7444 from being placed on the circuit canvas.</li>
<li>Sub-circuit can now be deleted with `DELETE` key, along with `BACKSPACE` used so far.</li>
<li>Fixed `Simulate` -> `Timing Diagram` not opening when using "Nimbus" look and feel.</li>
<li>Fixed pressing `CTRL`+`0` selecting the wrong element in the toolbar.</li>
<li>Fixed TTL 7485 `7485HdlGenerator` generating wrong HDL type.</li>
<li>Fixed TTL 74139, 7447 outputting inverted logic</li>
<li>Fixed TTL 74175, CLR inverted</li>
<li>Fixed TTL 7436 pin arrangement</li>
<li>Added TTL 74138: 3-line to 8-line decoder</li>
<li>Added TTL 74240, 74241, 74244: octal buffers with three-state outputs.</li>
<li>Added TTL 74245: octal bus transceivers with three-state outputs.</li>
<li>Moved TTL 74266 to 747266, correctly reimplemented 74266 with open-collector outputs.</li>
<li>Fixed TTL 74165, correct order of inputs, load asynchronously</li>
<li>Added TTL 74166: 8-bit parallel-to-serial shift register with clear</li>
<li>Removed fixed LM_Licence setting</li>
</ul>
</description>
</release>
<release version="3.7.2" date="2021-11-09">
<description>
<ul>
<li>Fixed Preferences/Window "Reset window layout to defaults" not doing much.</li>
<li>Fixed Gradle builder failing to compile LSe if sources were not checked out from Git.</li>
<li>You can now swap the placement of main canvas and component tree/properties pane.</li>
<li>Several bug fixes.</li>
</ul>
</description>
</release>
<release version="3.7.1" date="2021-10-21">
<description>
<ul>
<li>Logisim has now an internal font-chooser to comply to the font-values used.</li>
<li>Several bug fixes.</li>
</ul>
</description>
</release>
<release version="3.7.0" date="2021-10-12">
<description>
<ul>
<li>Reworked the slider component in the I/O extra library.</li>
<li>Tick clock frequency display moved to left corner. It's also bigger and text color is configurable.</li>
<li>Completely rewritten command line argument parser:</li>
<li>All options have both short and long version now,</li>
<li>All long arguments require `--` prefix i.e. `--version`,</li>
<li>All short arguments require single `-` as prefix i.e. `-v`,</li>
<li>`-clearprefs` is now `--clear-prefs`,</li>
<li>`-clearprops` option is removed (use `--clear-prefs` instead),</li>
<li>`-geom` is now `--geometry`,</li>
<li>`-nosplash` is now `--no-splash` or `-ns`,</li>
<li>`-sub` is now `--substitute` or `-s`,</li>
<li>`-testvector` is now `--test-vector` or `-w`,</li>
<li>`-test-fpga-implementation` is now `--test-fpga` or `-f`,</li>
<li>`-questa` is removed.</li>
<li>PortIO HDL generator and component bug-fixed.</li>
<li>Cleanup/rework of the HDL-generation.</li>
<li>Each circuit stores/restores the last board used for Download (handy for templates to give to students)</li>
<li>Fixed startup crash related to incorrectly localized date format.</li>
<li>Added a setting to select lower- or upper-case VHDL keywords.</li>
<li>Added project export feature.</li>
<li>Cleaned-up the written .circ file.</li>
</ul>
</description>
</release>
<release version="3.6.1" date="2021-09-27">
<description>
<ul>
<li>Fixed bug in LED-array</li>
</ul>
</description>
</release>
<release version="3.6.0" date="2021-09-05">
<description>
<ul>
<li>Introducing project logo.</li>
<li>Fixed project loader to correctly handle hex values with a 1 in bit 63rd.</li>
<li>Added TTL74x34 hex buffer gate.</li>
<li>Made pins' tooltips more descriptive for 74161.</li>
<li>Added new component LED Bar.</li>
<li>Added 74157 and 74158: Quad 2-line to1-line selectors.</li>
<li>Added option to configure canvas' and grid's colors.</li>
<li>Added DIP switch state visual feedback for ON state.</li>
<li>Augmented direction verbal labels (East, North, etc), with corresponding arrow symbols.</li>
<li>Application title string now adds app name/version at the very end of the title.</li>
<li>Added option to configure size of connection pin markers.</li>
<li>Added TTL 74x139: dual 2-line to 4-lines decoders.</li>
<li>Fixed missing port on DotMatrix.</li>
<li>Combined `Select Location` from Plexers and `Gate Location` from Wiring to one attribute.</li>
<li>comparability for Transistors and Transmission Gates.
When opening old .circ files, they will have the default `Select Location` ("Bottom/Left").</li>
<li>Replace DarkLaf with FlatLaf for better compatibility.</li>
<li>Adds "Rotate Left" context menu action.</li>
<li>Display "Too few inputs for table" if Karnaugh Map has only 1 input.</li>
<li>HexDisplay is stays blank if no valid data is fed instead of showing "H" [#365].</li>
<li>Project's "Dirty" (unsaved) state is now also reflected by adding `*` marker to the window title.</li>
<li>Support for `AnimatedIcon` has been completely removed.</li>
<li>Canvas Zoom controls new offer wider range of zoom and three level of granularity.</li>
<li>Added predefined quick zoom buttons.</li>
<li>Tons of code cleanup and internal improvements.</li>
<li>Added duplicated component placement on same location refusal</li>
<li>Fixed pin duplication on load in case a custom apearance is used for a circuit</li>
<li>Added LED-array support for FPGA-boards</li>
<li>Improved partial placement on FPGA-boards for multi-pin components</li>
<li>Fixed several small bugs</li>
<li>Each circuit will now remember, restore, and save:</li>
<li>The last tick-frequency used for simulation</li>
<li>The last download frequency used</li>
<li>Removed obsolete VHDL-Architecture attribute from circuit</li>
</ul>
</description>
</release>
<release version="3.5.0" date="2021-05-25">
<description>
<ul>
<li>Many code-cleanups, bug fixes and again the chronogram.</li>
</ul>
</description>
</release>
<release version="3.4.2" date="2021-02-19"/>
<release version="3.4.1" date="2020-12-25"/>
<release version="3.3.0" date="2020-01-09"/>
</releases>
<content_rating type="oars-1.1"/>
</component>