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Commit a6077e7

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eda: introduce board type
1 parent c4cc7f5 commit a6077e7

11 files changed

+1747
-1689
lines changed

‎eda/board.go

+1,525
Large diffs are not rendered by default.

‎eda/cfg.go

+1-5
Original file line numberDiff line numberDiff line change
@@ -87,9 +87,6 @@ type config struct {
8787
cshaper uint32 // capacity shaper
8888

8989
db dbConfig // configuration from tmv-db
90-
91-
buf [szCfgHR]byte
92-
data []byte
9390
}
9491

9592
daq struct {
@@ -126,7 +123,6 @@ func newConfig() config {
126123
cfg.hr.db = newDbConfig()
127124
cfg.hr.cshaper = 3
128125
cfg.daq.mode = "dcc"
129-
cfg.hr.data = cfg.hr.buf[4:]
130126
return cfg
131127
}
132128

@@ -161,7 +157,7 @@ func (dev *Device) configASICs(dif uint8) error {
161157
n = len(cfg)
162158
)
163159
for i, v := range cfg {
164-
dev.hrscSetBit(ihr, uint32(n-1-i), uint32(v))
160+
dev.brd.hrscSetBit(ihr, uint32(n-1-i), uint32(v))
165161
}
166162
}
167163
return nil

‎eda/cfg_test.go

+37-37
Original file line numberDiff line numberDiff line change
@@ -68,8 +68,8 @@ func TestCompareConfig(t *testing.T) {
6868
for i := range asics {
6969
var (
7070
ihr = (nHR - 1 - i) * nBytesCfgHR
71-
buf1 = devDB.cfg.hr.data[ihr : ihr+nBytesCfgHR]
72-
buf2 = devCSV.cfg.hr.data[ihr : ihr+nBytesCfgHR]
71+
buf1 = devDB.brd.sli[ihr : ihr+nBytesCfgHR]
72+
buf2 = devCSV.brd.sli[ihr : ihr+nBytesCfgHR]
7373
)
7474
if !bytes.Equal(buf1, buf2) {
7575
t.Errorf("asic-%d: hr-data NOT OK", i)
@@ -83,9 +83,9 @@ func TestCompareConfig(t *testing.T) {
8383
func testCfgWithDB(dev *Device, asics []conddb.ASIC, rshaper uint32, rfms []int) error {
8484
WithRShaper(rshaper)(&dev.cfg)
8585
dev.cfg.hr.cshaper = 3
86-
dev.cfg.hr.data = dev.cfg.hr.buf[4:]
8786
dev.cfg.hr.db = newDbConfig()
8887
dev.rfms = rfms
88+
dev.brd = newBoard(dev.msg)
8989

9090
{
9191
rfmID := asics[0].DIFID
@@ -95,22 +95,22 @@ func testCfgWithDB(dev *Device, asics []conddb.ASIC, rshaper uint32, rfms []int)
9595
return fmt.Errorf("could not configure ASICs for rfm=%d: %w", rfmID, err)
9696
}
9797
}
98-
dev.hrscSetBit(0, 854, 0)
98+
dev.brd.hrscSetBit(0, 854, 0)
9999

100-
dev.hrscSetRShaper(0, dev.cfg.hr.rshaper)
101-
dev.hrscSetCShaper(0, dev.cfg.hr.cshaper)
100+
dev.brd.hrscSetRShaper(0, dev.cfg.hr.rshaper)
101+
dev.brd.hrscSetCShaper(0, dev.cfg.hr.cshaper)
102102

103-
dev.hrscCopyConf(1, 0)
104-
dev.hrscCopyConf(2, 0)
105-
dev.hrscCopyConf(3, 0)
106-
dev.hrscCopyConf(4, 0)
107-
dev.hrscCopyConf(5, 0)
108-
dev.hrscCopyConf(6, 0)
109-
dev.hrscCopyConf(7, 0)
103+
dev.brd.hrscCopyConf(1, 0)
104+
dev.brd.hrscCopyConf(2, 0)
105+
dev.brd.hrscCopyConf(3, 0)
106+
dev.brd.hrscCopyConf(4, 0)
107+
dev.brd.hrscCopyConf(5, 0)
108+
dev.brd.hrscCopyConf(6, 0)
109+
dev.brd.hrscCopyConf(7, 0)
110110

111111
// set chip IDs
112112
for hr := uint32(0); hr < nHR; hr++ {
113-
dev.hrscSetChipID(hr, hr+1)
113+
dev.brd.hrscSetChipID(hr, hr+1)
114114
}
115115

116116
for i := range dev.rfms {
@@ -122,12 +122,12 @@ func testCfgWithDB(dev *Device, asics []conddb.ASIC, rshaper uint32, rfms []int)
122122
m2 := bitU64(asics[hr].Mask2, ch)
123123

124124
mask := uint32(m0 | m1<<1 | m2<<2)
125-
dev.hrscSetMask(hr, ch, mask)
125+
dev.brd.hrscSetMask(hr, ch, mask)
126126
}
127127

128-
dev.hrscSetDAC0(hr, uint32(asics[hr].B0))
129-
dev.hrscSetDAC1(hr, uint32(asics[hr].B1))
130-
dev.hrscSetDAC2(hr, uint32(asics[hr].B2))
128+
dev.brd.hrscSetDAC0(hr, uint32(asics[hr].B0))
129+
dev.brd.hrscSetDAC1(hr, uint32(asics[hr].B1))
130+
dev.brd.hrscSetDAC2(hr, uint32(asics[hr].B2))
131131

132132
for ch := uint32(0); ch < nChans; ch++ {
133133
v, err := strconv.ParseUint(string(asics[hr].PreAmpGain[2*ch:2*ch+2]), 16, 8)
@@ -136,7 +136,7 @@ func testCfgWithDB(dev *Device, asics []conddb.ASIC, rshaper uint32, rfms []int)
136136
}
137137
gain := uint32(v)
138138
dev.cfg.preamp.gains[nChans*(nHR*rfm+hr)+ch] = gain
139-
dev.hrscSetPreAmp(hr, ch, gain)
139+
dev.brd.hrscSetPreAmp(hr, ch, gain)
140140
}
141141
}
142142
}
@@ -149,10 +149,10 @@ func testCfgWithCSV(dev *Device, thresh, rshaper uint32, rfms []int) error {
149149
WithRShaper(rshaper)(&dev.cfg)
150150
dev.cfg.hr.db = newDbConfig()
151151
dev.cfg.hr.cshaper = 3
152-
dev.cfg.hr.data = dev.cfg.hr.buf[4:]
153152
dev.rfms = rfms
153+
dev.brd = newBoard(dev.msg)
154154

155-
err := dev.hrscReadConf(dev.cfg.hr.fname, 0)
155+
err := dev.brd.hrscReadConf(dev.cfg.hr.fname, 0)
156156
if err != nil {
157157
return fmt.Errorf("eda: could load single-HR configuration file: %w", err)
158158
}
@@ -173,22 +173,22 @@ func testCfgWithCSV(dev *Device, thresh, rshaper uint32, rfms []int) error {
173173
}
174174

175175
// disable trig_out output pin (RFM v1 coupling problem)
176-
dev.hrscSetBit(0, 854, 0)
176+
dev.brd.hrscSetBit(0, 854, 0)
177177

178-
dev.hrscSetRShaper(0, dev.cfg.hr.rshaper)
179-
dev.hrscSetCShaper(0, dev.cfg.hr.cshaper)
178+
dev.brd.hrscSetRShaper(0, dev.cfg.hr.rshaper)
179+
dev.brd.hrscSetCShaper(0, dev.cfg.hr.cshaper)
180180

181-
dev.hrscCopyConf(1, 0)
182-
dev.hrscCopyConf(2, 0)
183-
dev.hrscCopyConf(3, 0)
184-
dev.hrscCopyConf(4, 0)
185-
dev.hrscCopyConf(5, 0)
186-
dev.hrscCopyConf(6, 0)
187-
dev.hrscCopyConf(7, 0)
181+
dev.brd.hrscCopyConf(1, 0)
182+
dev.brd.hrscCopyConf(2, 0)
183+
dev.brd.hrscCopyConf(3, 0)
184+
dev.brd.hrscCopyConf(4, 0)
185+
dev.brd.hrscCopyConf(5, 0)
186+
dev.brd.hrscCopyConf(6, 0)
187+
dev.brd.hrscCopyConf(7, 0)
188188

189189
// set chip IDs
190190
for hr := uint32(0); hr < nHR; hr++ {
191-
dev.hrscSetChipID(hr, hr+1)
191+
dev.brd.hrscSetChipID(hr, hr+1)
192192
}
193193

194194
// for each active RFM, tune the configuration and send it.
@@ -197,7 +197,7 @@ func testCfgWithCSV(dev *Device, thresh, rshaper uint32, rfms []int) error {
197197
for hr := uint32(0); hr < nHR; hr++ {
198198
for ch := uint32(0); ch < nChans; ch++ {
199199
mask := dev.cfg.mask.table[nChans*(nHR*uint32(rfm)+hr)+ch]
200-
dev.hrscSetMask(hr, ch, mask)
200+
dev.brd.hrscSetMask(hr, ch, mask)
201201
}
202202
}
203203

@@ -210,15 +210,15 @@ func testCfgWithCSV(dev *Device, thresh, rshaper uint32, rfms []int) error {
210210
th0 := dev.cfg.daq.floor[3*(nHR*uint32(rfm)+hr)+0]
211211
th1 := dev.cfg.daq.floor[3*(nHR*uint32(rfm)+hr)+1]
212212
th2 := dev.cfg.daq.floor[3*(nHR*uint32(rfm)+hr)+2]
213-
dev.hrscSetDAC0(hr, th0)
214-
dev.hrscSetDAC1(hr, th1)
215-
dev.hrscSetDAC2(hr, th2)
213+
dev.brd.hrscSetDAC0(hr, th0)
214+
dev.brd.hrscSetDAC1(hr, th1)
215+
dev.brd.hrscSetDAC2(hr, th2)
216216
}
217217

218218
for hr := uint32(0); hr < nHR; hr++ {
219219
for ch := uint32(0); ch < nChans; ch++ {
220220
gain := dev.cfg.preamp.gains[nChans*hr+ch]
221-
dev.hrscSetPreAmp(hr, ch, gain)
221+
dev.brd.hrscSetPreAmp(hr, ch, gain)
222222
}
223223
}
224224

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