Added PREFETCHW and improved README

Author: raphaelcohn

README.md

@@ -2,7 +2,7 @@
 
 [assembler] provides a fast, run-time assembler for x86-64 long mode instructions using function calls for Rust. In using a design that Rust's release build optimizations can work effectively with, it provides the ability to embed the assembled machine code instructions as templates inside Rust code, so as to make specialized code generation as fast as possible. It is particularly suited to being the backend to a JIT.
 
-This technique differs to that used in [dynasm], but was driven by the need to programmatically generate complex assembler to optimize message filters at runtime. The code for instruction generation is inspired by that from Stanford's [x64asm].
+This technique differs to that used in [dynasm], but was driven by the need to programmatically generate complex assembler to optimize message filter functions at runtime. The code for the instruction generation is inspired by that from Stanford's [x64asm].
 
 As a consequence, jump (and similar) instruction relaxation is not performed, ie all jumps use 32-bit displacements instead of being optimized for 8-bit displacements. Additional dedicated support is also included (eg `BitMemory`) to work with code that might be placed outside of the first 2Gb (eg on Mac OS X).
 
@@ -33,18 +33,23 @@ Add the crate `assembler` to your Cargo.toml file as usual and add an `extern cr
 
 Pull requests implementing these would be much appreciated\*.
 * Any support at all of the AVX512 instructions and associated memory operands.
-* 3D Now! (eg `PREFETCHW`).
+* 3D Now!'s `PREFETCH`.
 * Support for using the debug, control and bound registers.
 * `if` clauses inside some instruction generation sequences to output more efficient known register forms, eg those that default to `RAX`.
 
 
 <sup>\* With copyright assignment to the project, of course!</sup>
 
 
+## Possible
+
+* The instruction pointer should be an `u64` rather than `usize` so that assembling 64-bit code on 32-bit platforms is possible. That said, the main use of this project is to generate assembler to be used at runtime.
+
+
 ### Unlikely to be added
 
-* XOP (deprecated)
-* AMD's bit manipulation
+* Intel Xeon Phi specific instructions.
+* AMD's deprecated bit manipulation instructions and `XOP` encoding prefix.
 * Instruction relaxation; requires using a linked list to manage 'bundles' of instructions
 * Dynamic relocation
 * 32-bit compatibility mode
@@ -53,7 +58,7 @@ Pull requests implementing these would be much appreciated\*.
 
 ## Licensing
 
-The license for this project is Affero GNU Public License 3.0 (AGPL-3.0). Note that very early, unreleased versions of used source code forked from the [dynasm] project; this code is no longer in use within the code base. However, the authors of [assembler] are grateful to the authors of [dynasm] for the inspiration behind this work.
+The license for this project is Affero GNU Public License 3.0 (AGPL-3.0). Note that very early, unreleased versions used source code forked from the [dynasm] project; this code is no longer in use within the code base. However, the authors of [assembler] are grateful to the authors of [dynasm] for the inspiration behind this work.
 
 
 [assembler]: https://github.com/lemonrock/assembler "assembler GitHub page"

workspace/assembler/Cargo.toml

@@ -15,7 +15,7 @@ exclude = ["*"]
 include = ["README.md", "LICENSE", "COPYRIGHT", "src/**/*.rs", "Cargo.toml", "rustfmt.toml", "clippy.toml"]
 readme = "README.md"
 publish = true
-version = "0.7.1"
+version = "0.7.2"
 
 [dependencies]
 libc = "^0.2"

workspace/assembler/src/InstructionStream.instructions.rs

@@ -51969,6 +51969,37 @@ impl<'a> InstructionStream<'a>
 		// No label displacement.
 	}
 
+	/// Move data from `m8` closer to the processor in anticipation of a write.
+	///
+	/// Introduced with AMD's 3DNow! instructions.
+	#[inline(always)]
+	pub fn prefetchw_Any8BitMemory(&mut self, arg0: Any8BitMemory)
+	{
+		self.reserve_space_for_instruction();
+
+		// This is not a VEX encoded instruction.
+
+		// No `FWAIT` Prefix.
+
+		self.prefix_group2(arg0);
+
+		self.prefix_group4(arg0);
+
+		// No prefix group 3.
+
+		// No prefix group 1.
+
+		self.rex_2(arg0, 0x00);
+
+		self.opcode_2(0x0F, 0x0D);
+		
+		self.mod_rm_sib(arg0, Register64Bit::RCX);
+
+		// No displacement or immediate.
+
+		// No label displacement.
+	}
+
 	/// Computes the absolute differences of the packed unsigned byte integers from `mm2/m64` and `mm1`; differences are then summed to produce an unsigned word integer result.
 	#[inline(always)]
 	pub fn psadbw_MMRegister_Any64BitMemory(&mut self, arg0: MMRegister, arg1: Any64BitMemory)