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konradybciokonradybcio
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sm6375: Use C99 struct initialization
1 parent 8e00ed6 commit 9d01d16

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1 file changed

+151
-151
lines changed

1 file changed

+151
-151
lines changed

‎sm6375.c

Lines changed: 151 additions & 151 deletions
Original file line numberDiff line numberDiff line change
@@ -107,163 +107,163 @@ static struct debug_mux mc_cc = {
107107
};
108108

109109
static struct measure_clk sm6375_clocks[] = {
110-
{ "l3_clk", &cpu_cc, 0x41 },
111-
{ "perfcl_clk", &cpu_cc, 0x25 },
112-
{ "pwrcl_clk", &cpu_cc, 0x21 },
110+
{ .name = "l3_clk", .clk_mux = &cpu_cc, .mux = 0x41 },
111+
{ .name = "perfcl_clk", .clk_mux = &cpu_cc, .mux = 0x25 },
112+
{ .name = "pwrcl_clk", .clk_mux = &cpu_cc, .mux = 0x21 },
113113

114-
{ "gcc_ahb2phy_csi_clk", &gcc.mux, 0x67 },
115-
{ "gcc_ahb2phy_usb_clk", &gcc.mux, 0x68 },
116-
{ "gcc_bimc_gpu_axi_clk", &gcc.mux, 0x9d },
117-
{ "gcc_boot_rom_ahb_clk", &gcc.mux, 0x84 },
118-
{ "gcc_cam_throttle_nrt_clk", &gcc.mux, 0x4d },
119-
{ "gcc_cam_throttle_rt_clk", &gcc.mux, 0x4c },
120-
{ "gcc_camss_axi_clk", &gcc.mux, 0x154 },
121-
{ "gcc_camss_cci_0_clk", &gcc.mux, 0x151 },
122-
{ "gcc_camss_cci_1_clk", &gcc.mux, 0x152 },
123-
{ "gcc_camss_cphy_0_clk", &gcc.mux, 0x140 },
124-
{ "gcc_camss_cphy_1_clk", &gcc.mux, 0x141 },
125-
{ "gcc_camss_cphy_2_clk", &gcc.mux, 0x142 },
126-
{ "gcc_camss_cphy_3_clk", &gcc.mux, 0x143 },
127-
{ "gcc_camss_csi0phytimer_clk", &gcc.mux, 0x130 },
128-
{ "gcc_camss_csi1phytimer_clk", &gcc.mux, 0x131 },
129-
{ "gcc_camss_csi2phytimer_clk", &gcc.mux, 0x132 },
130-
{ "gcc_camss_csi3phytimer_clk", &gcc.mux, 0x133 },
131-
{ "gcc_camss_mclk0_clk", &gcc.mux, 0x134 },
132-
{ "gcc_camss_mclk1_clk", &gcc.mux, 0x135 },
133-
{ "gcc_camss_mclk2_clk", &gcc.mux, 0x136 },
134-
{ "gcc_camss_mclk3_clk", &gcc.mux, 0x137 },
135-
{ "gcc_camss_mclk4_clk", &gcc.mux, 0x138 },
136-
{ "gcc_camss_nrt_axi_clk", &gcc.mux, 0x158 },
137-
{ "gcc_camss_ope_ahb_clk", &gcc.mux, 0x150 },
138-
{ "gcc_camss_ope_clk", &gcc.mux, 0x14e },
139-
{ "gcc_camss_rt_axi_clk", &gcc.mux, 0x15a },
140-
{ "gcc_camss_tfe_0_clk", &gcc.mux, 0x139 },
141-
{ "gcc_camss_tfe_0_cphy_rx_clk", &gcc.mux, 0x13d },
142-
{ "gcc_camss_tfe_0_csid_clk", &gcc.mux, 0x144 },
143-
{ "gcc_camss_tfe_1_clk", &gcc.mux, 0x13a },
144-
{ "gcc_camss_tfe_1_cphy_rx_clk", &gcc.mux, 0x13e },
145-
{ "gcc_camss_tfe_1_csid_clk", &gcc.mux, 0x146 },
146-
{ "gcc_camss_tfe_2_clk", &gcc.mux, 0x13b },
147-
{ "gcc_camss_tfe_2_cphy_rx_clk", &gcc.mux, 0x13f },
148-
{ "gcc_camss_tfe_2_csid_clk", &gcc.mux, 0x148 },
149-
{ "gcc_camss_top_ahb_clk", &gcc.mux, 0x153 },
150-
{ "gcc_cfg_noc_usb3_prim_axi_clk", &gcc.mux, 0x1f },
151-
{ "gcc_disp_gpll0_div_clk_src", &gcc.mux, 0x48 },
152-
{ "gcc_disp_hf_axi_clk", &gcc.mux, 0x3e },
153-
{ "gcc_disp_sleep_clk", &gcc.mux, 0x4e },
154-
{ "gcc_disp_throttle_core_clk", &gcc.mux, 0x4a },
155-
{ "gcc_gp1_clk", &gcc.mux, 0xca },
156-
{ "gcc_gp2_clk", &gcc.mux, 0xcb },
157-
{ "gcc_gp3_clk", &gcc.mux, 0xcc },
158-
{ "gcc_gpu_gpll0_clk_src", &gcc.mux, 0xff },
159-
{ "gcc_gpu_gpll0_div_clk_src", &gcc.mux, 0x100 },
160-
{ "gcc_gpu_memnoc_gfx_clk", &gcc.mux, 0xfc },
161-
{ "gcc_gpu_snoc_dvm_gfx_clk", &gcc.mux, 0xfe },
162-
{ "gcc_gpu_throttle_core_clk", &gcc.mux, 0x103 },
163-
{ "gcc_pdm2_clk", &gcc.mux, 0x81 },
164-
{ "gcc_pdm_ahb_clk", &gcc.mux, 0x7f },
165-
{ "gcc_pdm_xo4_clk", &gcc.mux, 0x80 },
166-
{ "gcc_prng_ahb_clk", &gcc.mux, 0x82 },
167-
{ "gcc_qmip_camera_nrt_ahb_clk", &gcc.mux, 0x3b },
168-
{ "gcc_qmip_camera_rt_ahb_clk", &gcc.mux, 0x49 },
169-
{ "gcc_qmip_disp_ahb_clk", &gcc.mux, 0x3c },
170-
{ "gcc_qmip_gpu_cfg_ahb_clk", &gcc.mux, 0x101 },
171-
{ "gcc_qmip_video_vcodec_ahb_clk", &gcc.mux, 0x3a },
172-
{ "gcc_qupv3_wrap0_core_2x_clk", &gcc.mux, 0x6e },
173-
{ "gcc_qupv3_wrap0_core_clk", &gcc.mux, 0x6d },
174-
{ "gcc_qupv3_wrap0_s0_clk", &gcc.mux, 0x6f },
175-
{ "gcc_qupv3_wrap0_s1_clk", &gcc.mux, 0x70 },
176-
{ "gcc_qupv3_wrap0_s2_clk", &gcc.mux, 0x71 },
177-
{ "gcc_qupv3_wrap0_s3_clk", &gcc.mux, 0x72 },
178-
{ "gcc_qupv3_wrap0_s4_clk", &gcc.mux, 0x73 },
179-
{ "gcc_qupv3_wrap0_s5_clk", &gcc.mux, 0x74 },
180-
{ "gcc_qupv3_wrap1_core_2x_clk", &gcc.mux, 0x78 },
181-
{ "gcc_qupv3_wrap1_core_clk", &gcc.mux, 0x77 },
182-
{ "gcc_qupv3_wrap1_s0_clk", &gcc.mux, 0x79 },
183-
{ "gcc_qupv3_wrap1_s1_clk", &gcc.mux, 0x7a },
184-
{ "gcc_qupv3_wrap1_s2_clk", &gcc.mux, 0x7b },
185-
{ "gcc_qupv3_wrap1_s3_clk", &gcc.mux, 0x7c },
186-
{ "gcc_qupv3_wrap1_s5_clk", &gcc.mux, 0x7e },
187-
{ "gcc_qupv3_wrap_0_m_ahb_clk", &gcc.mux, 0x6b },
188-
{ "gcc_qupv3_wrap_0_s_ahb_clk", &gcc.mux, 0x6c },
189-
{ "gcc_sdcc1_ahb_clk", &gcc.mux, 0x108 },
190-
{ "gcc_sdcc1_apps_clk", &gcc.mux, 0x107 },
191-
{ "gcc_sdcc1_ice_core_clk", &gcc.mux, 0x109 },
192-
{ "gcc_sdcc2_ahb_clk", &gcc.mux, 0x6a },
193-
{ "gcc_sdcc2_apps_clk", &gcc.mux, 0x69 },
194-
{ "gcc_sys_noc_cpuss_ahb_clk", &gcc.mux, 0x9 },
195-
{ "gcc_sys_noc_ufs_phy_axi_clk", &gcc.mux, 0x1b },
196-
{ "gcc_sys_noc_usb3_prim_axi_clk", &gcc.mux, 0x1a },
197-
{ "gcc_ufs_phy_ahb_clk", &gcc.mux, 0x127 },
198-
{ "gcc_ufs_phy_axi_clk", &gcc.mux, 0x126 },
199-
{ "gcc_ufs_phy_ice_core_clk", &gcc.mux, 0x12d },
200-
{ "gcc_ufs_phy_phy_aux_clk", &gcc.mux, 0x12e },
201-
{ "gcc_ufs_phy_rx_symbol_0_clk", &gcc.mux, 0x129 },
202-
{ "gcc_ufs_phy_tx_symbol_0_clk", &gcc.mux, 0x128 },
203-
{ "gcc_ufs_phy_unipro_core_clk", &gcc.mux, 0x12c },
204-
{ "gcc_usb30_prim_master_clk", &gcc.mux, 0x5e },
205-
{ "gcc_usb30_prim_mock_utmi_clk", &gcc.mux, 0x60 },
206-
{ "gcc_usb30_prim_sleep_clk", &gcc.mux, 0x5f },
207-
{ "gcc_usb3_prim_phy_com_aux_clk", &gcc.mux, 0x61 },
208-
{ "gcc_usb3_prim_phy_pipe_clk", &gcc.mux, 0x62 },
209-
{ "gcc_vcodec0_axi_clk", &gcc.mux, 0x160 },
210-
{ "gcc_venus_ahb_clk", &gcc.mux, 0x161 },
211-
{ "gcc_venus_ctl_axi_clk", &gcc.mux, 0x15f },
212-
{ "gcc_video_axi0_clk", &gcc.mux, 0x3d },
213-
{ "gcc_video_throttle_core_clk", &gcc.mux, 0x4b },
214-
{ "gcc_video_vcodec0_sys_clk", &gcc.mux, 0x15d },
215-
{ "gcc_video_venus_ctl_clk", &gcc.mux, 0x15b },
216-
{ "gcc_video_xo_clk", &gcc.mux, 0x3f },
217-
{ "measure_only_cnoc_clk", &gcc.mux, 0x1d },
218-
{ "measure_only_gcc_camera_ahb_clk", &gcc.mux, 0x38 },
219-
{ "measure_only_gcc_camera_xo_clk", &gcc.mux, 0x40 },
220-
{ "measure_only_gcc_cpuss_gnoc_clk", &gcc.mux, 0xba },
221-
{ "measure_only_gcc_disp_ahb_clk", &gcc.mux, 0x39 },
222-
{ "measure_only_gcc_disp_xo_clk", &gcc.mux, 0x41 },
223-
{ "measure_only_gcc_gpu_cfg_ahb_clk", &gcc.mux, 0xf9 },
224-
{ "measure_only_gcc_qupv3_wrap1_s4_clk", &gcc.mux, 0x7d },
225-
{ "measure_only_gcc_qupv3_wrap_1_m_ahb_clk", &gcc.mux, 0x75 },
226-
{ "measure_only_gcc_qupv3_wrap_1_s_ahb_clk", &gcc.mux, 0x76 },
227-
{ "measure_only_gcc_video_ahb_clk", &gcc.mux, 0x37 },
228-
{ "measure_only_hwkm_ahb_clk", &gcc.mux, 0x166 },
229-
{ "measure_only_hwkm_km_core_clk", &gcc.mux, 0x167 },
230-
{ "measure_only_ipa_2x_clk", &gcc.mux, 0xd7 },
231-
{ "measure_only_pka_ahb_clk", &gcc.mux, 0x162 },
232-
{ "measure_only_pka_core_clk", &gcc.mux, 0x163 },
233-
{ "measure_only_snoc_clk", &gcc.mux, 0x7 },
114+
{ .name = "gcc_ahb2phy_csi_clk", .clk_mux = &gcc.mux, .mux = 0x67 },
115+
{ .name = "gcc_ahb2phy_usb_clk", .clk_mux = &gcc.mux, .mux = 0x68 },
116+
{ .name = "gcc_bimc_gpu_axi_clk", .clk_mux = &gcc.mux, .mux = 0x9d },
117+
{ .name = "gcc_boot_rom_ahb_clk", .clk_mux = &gcc.mux, .mux = 0x84 },
118+
{ .name = "gcc_cam_throttle_nrt_clk", .clk_mux = &gcc.mux, .mux = 0x4d },
119+
{ .name = "gcc_cam_throttle_rt_clk", .clk_mux = &gcc.mux, .mux = 0x4c },
120+
{ .name = "gcc_camss_axi_clk", .clk_mux = &gcc.mux, .mux = 0x154 },
121+
{ .name = "gcc_camss_cci_0_clk", .clk_mux = &gcc.mux, .mux = 0x151 },
122+
{ .name = "gcc_camss_cci_1_clk", .clk_mux = &gcc.mux, .mux = 0x152 },
123+
{ .name = "gcc_camss_cphy_0_clk", .clk_mux = &gcc.mux, .mux = 0x140 },
124+
{ .name = "gcc_camss_cphy_1_clk", .clk_mux = &gcc.mux, .mux = 0x141 },
125+
{ .name = "gcc_camss_cphy_2_clk", .clk_mux = &gcc.mux, .mux = 0x142 },
126+
{ .name = "gcc_camss_cphy_3_clk", .clk_mux = &gcc.mux, .mux = 0x143 },
127+
{ .name = "gcc_camss_csi0phytimer_clk", .clk_mux = &gcc.mux, .mux = 0x130 },
128+
{ .name = "gcc_camss_csi1phytimer_clk", .clk_mux = &gcc.mux, .mux = 0x131 },
129+
{ .name = "gcc_camss_csi2phytimer_clk", .clk_mux = &gcc.mux, .mux = 0x132 },
130+
{ .name = "gcc_camss_csi3phytimer_clk", .clk_mux = &gcc.mux, .mux = 0x133 },
131+
{ .name = "gcc_camss_mclk0_clk", .clk_mux = &gcc.mux, .mux = 0x134 },
132+
{ .name = "gcc_camss_mclk1_clk", .clk_mux = &gcc.mux, .mux = 0x135 },
133+
{ .name = "gcc_camss_mclk2_clk", .clk_mux = &gcc.mux, .mux = 0x136 },
134+
{ .name = "gcc_camss_mclk3_clk", .clk_mux = &gcc.mux, .mux = 0x137 },
135+
{ .name = "gcc_camss_mclk4_clk", .clk_mux = &gcc.mux, .mux = 0x138 },
136+
{ .name = "gcc_camss_nrt_axi_clk", .clk_mux = &gcc.mux, .mux = 0x158 },
137+
{ .name = "gcc_camss_ope_ahb_clk", .clk_mux = &gcc.mux, .mux = 0x150 },
138+
{ .name = "gcc_camss_ope_clk", .clk_mux = &gcc.mux, .mux = 0x14e },
139+
{ .name = "gcc_camss_rt_axi_clk", .clk_mux = &gcc.mux, .mux = 0x15a },
140+
{ .name = "gcc_camss_tfe_0_clk", .clk_mux = &gcc.mux, .mux = 0x139 },
141+
{ .name = "gcc_camss_tfe_0_cphy_rx_clk", .clk_mux = &gcc.mux, .mux = 0x13d },
142+
{ .name = "gcc_camss_tfe_0_csid_clk", .clk_mux = &gcc.mux, .mux = 0x144 },
143+
{ .name = "gcc_camss_tfe_1_clk", .clk_mux = &gcc.mux, .mux = 0x13a },
144+
{ .name = "gcc_camss_tfe_1_cphy_rx_clk", .clk_mux = &gcc.mux, .mux = 0x13e },
145+
{ .name = "gcc_camss_tfe_1_csid_clk", .clk_mux = &gcc.mux, .mux = 0x146 },
146+
{ .name = "gcc_camss_tfe_2_clk", .clk_mux = &gcc.mux, .mux = 0x13b },
147+
{ .name = "gcc_camss_tfe_2_cphy_rx_clk", .clk_mux = &gcc.mux, .mux = 0x13f },
148+
{ .name = "gcc_camss_tfe_2_csid_clk", .clk_mux = &gcc.mux, .mux = 0x148 },
149+
{ .name = "gcc_camss_top_ahb_clk", .clk_mux = &gcc.mux, .mux = 0x153 },
150+
{ .name = "gcc_cfg_noc_usb3_prim_axi_clk", .clk_mux = &gcc.mux, .mux = 0x1f },
151+
{ .name = "gcc_disp_gpll0_div_clk_src", .clk_mux = &gcc.mux, .mux = 0x48 },
152+
{ .name = "gcc_disp_hf_axi_clk", .clk_mux = &gcc.mux, .mux = 0x3e },
153+
{ .name = "gcc_disp_sleep_clk", .clk_mux = &gcc.mux, .mux = 0x4e },
154+
{ .name = "gcc_disp_throttle_core_clk", .clk_mux = &gcc.mux, .mux = 0x4a },
155+
{ .name = "gcc_gp1_clk", .clk_mux = &gcc.mux, .mux = 0xca },
156+
{ .name = "gcc_gp2_clk", .clk_mux = &gcc.mux, .mux = 0xcb },
157+
{ .name = "gcc_gp3_clk", .clk_mux = &gcc.mux, .mux = 0xcc },
158+
{ .name = "gcc_gpu_gpll0_clk_src", .clk_mux = &gcc.mux, .mux = 0xff },
159+
{ .name = "gcc_gpu_gpll0_div_clk_src", .clk_mux = &gcc.mux, .mux = 0x100 },
160+
{ .name = "gcc_gpu_memnoc_gfx_clk", .clk_mux = &gcc.mux, .mux = 0xfc },
161+
{ .name = "gcc_gpu_snoc_dvm_gfx_clk", .clk_mux = &gcc.mux, .mux = 0xfe },
162+
{ .name = "gcc_gpu_throttle_core_clk", .clk_mux = &gcc.mux, .mux = 0x103 },
163+
{ .name = "gcc_pdm2_clk", .clk_mux = &gcc.mux, .mux = 0x81 },
164+
{ .name = "gcc_pdm_ahb_clk", .clk_mux = &gcc.mux, .mux = 0x7f },
165+
{ .name = "gcc_pdm_xo4_clk", .clk_mux = &gcc.mux, .mux = 0x80 },
166+
{ .name = "gcc_prng_ahb_clk", .clk_mux = &gcc.mux, .mux = 0x82 },
167+
{ .name = "gcc_qmip_camera_nrt_ahb_clk", .clk_mux = &gcc.mux, .mux = 0x3b },
168+
{ .name = "gcc_qmip_camera_rt_ahb_clk", .clk_mux = &gcc.mux, .mux = 0x49 },
169+
{ .name = "gcc_qmip_disp_ahb_clk", .clk_mux = &gcc.mux, .mux = 0x3c },
170+
{ .name = "gcc_qmip_gpu_cfg_ahb_clk", .clk_mux = &gcc.mux, .mux = 0x101 },
171+
{ .name = "gcc_qmip_video_vcodec_ahb_clk", .clk_mux = &gcc.mux, .mux = 0x3a },
172+
{ .name = "gcc_qupv3_wrap0_core_2x_clk", .clk_mux = &gcc.mux, .mux = 0x6e },
173+
{ .name = "gcc_qupv3_wrap0_core_clk", .clk_mux = &gcc.mux, .mux = 0x6d },
174+
{ .name = "gcc_qupv3_wrap0_s0_clk", .clk_mux = &gcc.mux, .mux = 0x6f },
175+
{ .name = "gcc_qupv3_wrap0_s1_clk", .clk_mux = &gcc.mux, .mux = 0x70 },
176+
{ .name = "gcc_qupv3_wrap0_s2_clk", .clk_mux = &gcc.mux, .mux = 0x71 },
177+
{ .name = "gcc_qupv3_wrap0_s3_clk", .clk_mux = &gcc.mux, .mux = 0x72 },
178+
{ .name = "gcc_qupv3_wrap0_s4_clk", .clk_mux = &gcc.mux, .mux = 0x73 },
179+
{ .name = "gcc_qupv3_wrap0_s5_clk", .clk_mux = &gcc.mux, .mux = 0x74 },
180+
{ .name = "gcc_qupv3_wrap1_core_2x_clk", .clk_mux = &gcc.mux, .mux = 0x78 },
181+
{ .name = "gcc_qupv3_wrap1_core_clk", .clk_mux = &gcc.mux, .mux = 0x77 },
182+
{ .name = "gcc_qupv3_wrap1_s0_clk", .clk_mux = &gcc.mux, .mux = 0x79 },
183+
{ .name = "gcc_qupv3_wrap1_s1_clk", .clk_mux = &gcc.mux, .mux = 0x7a },
184+
{ .name = "gcc_qupv3_wrap1_s2_clk", .clk_mux = &gcc.mux, .mux = 0x7b },
185+
{ .name = "gcc_qupv3_wrap1_s3_clk", .clk_mux = &gcc.mux, .mux = 0x7c },
186+
{ .name = "gcc_qupv3_wrap1_s5_clk", .clk_mux = &gcc.mux, .mux = 0x7e },
187+
{ .name = "gcc_qupv3_wrap_0_m_ahb_clk", .clk_mux = &gcc.mux, .mux = 0x6b },
188+
{ .name = "gcc_qupv3_wrap_0_s_ahb_clk", .clk_mux = &gcc.mux, .mux = 0x6c },
189+
{ .name = "gcc_sdcc1_ahb_clk", .clk_mux = &gcc.mux, .mux = 0x108 },
190+
{ .name = "gcc_sdcc1_apps_clk", .clk_mux = &gcc.mux, .mux = 0x107 },
191+
{ .name = "gcc_sdcc1_ice_core_clk", .clk_mux = &gcc.mux, .mux = 0x109 },
192+
{ .name = "gcc_sdcc2_ahb_clk", .clk_mux = &gcc.mux, .mux = 0x6a },
193+
{ .name = "gcc_sdcc2_apps_clk", .clk_mux = &gcc.mux, .mux = 0x69 },
194+
{ .name = "gcc_sys_noc_cpuss_ahb_clk", .clk_mux = &gcc.mux, .mux = 0x9 },
195+
{ .name = "gcc_sys_noc_ufs_phy_axi_clk", .clk_mux = &gcc.mux, .mux = 0x1b },
196+
{ .name = "gcc_sys_noc_usb3_prim_axi_clk", .clk_mux = &gcc.mux, .mux = 0x1a },
197+
{ .name = "gcc_ufs_phy_ahb_clk", .clk_mux = &gcc.mux, .mux = 0x127 },
198+
{ .name = "gcc_ufs_phy_axi_clk", .clk_mux = &gcc.mux, .mux = 0x126 },
199+
{ .name = "gcc_ufs_phy_ice_core_clk", .clk_mux = &gcc.mux, .mux = 0x12d },
200+
{ .name = "gcc_ufs_phy_phy_aux_clk", .clk_mux = &gcc.mux, .mux = 0x12e },
201+
{ .name = "gcc_ufs_phy_rx_symbol_0_clk", .clk_mux = &gcc.mux, .mux = 0x129 },
202+
{ .name = "gcc_ufs_phy_tx_symbol_0_clk", .clk_mux = &gcc.mux, .mux = 0x128 },
203+
{ .name = "gcc_ufs_phy_unipro_core_clk", .clk_mux = &gcc.mux, .mux = 0x12c },
204+
{ .name = "gcc_usb30_prim_master_clk", .clk_mux = &gcc.mux, .mux = 0x5e },
205+
{ .name = "gcc_usb30_prim_mock_utmi_clk", .clk_mux = &gcc.mux, .mux = 0x60 },
206+
{ .name = "gcc_usb30_prim_sleep_clk", .clk_mux = &gcc.mux, .mux = 0x5f },
207+
{ .name = "gcc_usb3_prim_phy_com_aux_clk", .clk_mux = &gcc.mux, .mux = 0x61 },
208+
{ .name = "gcc_usb3_prim_phy_pipe_clk", .clk_mux = &gcc.mux, .mux = 0x62 },
209+
{ .name = "gcc_vcodec0_axi_clk", .clk_mux = &gcc.mux, .mux = 0x160 },
210+
{ .name = "gcc_venus_ahb_clk", .clk_mux = &gcc.mux, .mux = 0x161 },
211+
{ .name = "gcc_venus_ctl_axi_clk", .clk_mux = &gcc.mux, .mux = 0x15f },
212+
{ .name = "gcc_video_axi0_clk", .clk_mux = &gcc.mux, .mux = 0x3d },
213+
{ .name = "gcc_video_throttle_core_clk", .clk_mux = &gcc.mux, .mux = 0x4b },
214+
{ .name = "gcc_video_vcodec0_sys_clk", .clk_mux = &gcc.mux, .mux = 0x15d },
215+
{ .name = "gcc_video_venus_ctl_clk", .clk_mux = &gcc.mux, .mux = 0x15b },
216+
{ .name = "gcc_video_xo_clk", .clk_mux = &gcc.mux, .mux = 0x3f },
217+
{ .name = "measure_only_cnoc_clk", .clk_mux = &gcc.mux, .mux = 0x1d },
218+
{ .name = "measure_only_gcc_camera_ahb_clk", .clk_mux = &gcc.mux, .mux = 0x38 },
219+
{ .name = "measure_only_gcc_camera_xo_clk", .clk_mux = &gcc.mux, .mux = 0x40 },
220+
{ .name = "measure_only_gcc_cpuss_gnoc_clk", .clk_mux = &gcc.mux, .mux = 0xba },
221+
{ .name = "measure_only_gcc_disp_ahb_clk", .clk_mux = &gcc.mux, .mux = 0x39 },
222+
{ .name = "measure_only_gcc_disp_xo_clk", .clk_mux = &gcc.mux, .mux = 0x41 },
223+
{ .name = "measure_only_gcc_gpu_cfg_ahb_clk", .clk_mux = &gcc.mux, .mux = 0xf9 },
224+
{ .name = "measure_only_gcc_qupv3_wrap1_s4_clk", .clk_mux = &gcc.mux, .mux = 0x7d },
225+
{ .name = "measure_only_gcc_qupv3_wrap_1_m_ahb_clk", .clk_mux = &gcc.mux, .mux = 0x75 },
226+
{ .name = "measure_only_gcc_qupv3_wrap_1_s_ahb_clk", .clk_mux = &gcc.mux, .mux = 0x76 },
227+
{ .name = "measure_only_gcc_video_ahb_clk", .clk_mux = &gcc.mux, .mux = 0x37 },
228+
{ .name = "measure_only_hwkm_ahb_clk", .clk_mux = &gcc.mux, .mux = 0x166 },
229+
{ .name = "measure_only_hwkm_km_core_clk", .clk_mux = &gcc.mux, .mux = 0x167 },
230+
{ .name = "measure_only_ipa_2x_clk", .clk_mux = &gcc.mux, .mux = 0xd7 },
231+
{ .name = "measure_only_pka_ahb_clk", .clk_mux = &gcc.mux, .mux = 0x162 },
232+
{ .name = "measure_only_pka_core_clk", .clk_mux = &gcc.mux, .mux = 0x163 },
233+
{ .name = "measure_only_snoc_clk", .clk_mux = &gcc.mux, .mux = 0x7 },
234234

235-
{ "disp_cc_mdss_ahb_clk", &disp_cc, 0x14 },
236-
{ "disp_cc_mdss_byte0_clk", &disp_cc, 0xc },
237-
{ "disp_cc_mdss_byte0_intf_clk", &disp_cc, 0xd },
238-
{ "disp_cc_mdss_esc0_clk", &disp_cc, 0xe },
239-
{ "disp_cc_mdss_mdp_clk", &disp_cc, 0x8 },
240-
{ "disp_cc_mdss_mdp_lut_clk", &disp_cc, 0xa },
241-
{ "disp_cc_mdss_non_gdsc_ahb_clk", &disp_cc, 0x15 },
242-
{ "disp_cc_mdss_pclk0_clk", &disp_cc, 0x7 },
243-
{ "disp_cc_mdss_rot_clk", &disp_cc, 0x9 },
244-
{ "disp_cc_mdss_rscc_ahb_clk", &disp_cc, 0x17 },
245-
{ "disp_cc_mdss_rscc_vsync_clk", &disp_cc, 0x16 },
246-
{ "disp_cc_mdss_vsync_clk", &disp_cc, 0xb },
247-
{ "measure_only_disp_cc_sleep_clk", &disp_cc, 0x1d },
248-
{ "measure_only_disp_cc_xo_clk", &disp_cc, 0x1e },
235+
{ .name = "disp_cc_mdss_ahb_clk", .clk_mux = &disp_cc, .mux = 0x14 },
236+
{ .name = "disp_cc_mdss_byte0_clk", .clk_mux = &disp_cc, .mux = 0xc },
237+
{ .name = "disp_cc_mdss_byte0_intf_clk", .clk_mux = &disp_cc, .mux = 0xd },
238+
{ .name = "disp_cc_mdss_esc0_clk", .clk_mux = &disp_cc, .mux = 0xe },
239+
{ .name = "disp_cc_mdss_mdp_clk", .clk_mux = &disp_cc, .mux = 0x8 },
240+
{ .name = "disp_cc_mdss_mdp_lut_clk", .clk_mux = &disp_cc, .mux = 0xa },
241+
{ .name = "disp_cc_mdss_non_gdsc_ahb_clk", .clk_mux = &disp_cc, .mux = 0x15 },
242+
{ .name = "disp_cc_mdss_pclk0_clk", .clk_mux = &disp_cc, .mux = 0x7 },
243+
{ .name = "disp_cc_mdss_rot_clk", .clk_mux = &disp_cc, .mux = 0x9 },
244+
{ .name = "disp_cc_mdss_rscc_ahb_clk", .clk_mux = &disp_cc, .mux = 0x17 },
245+
{ .name = "disp_cc_mdss_rscc_vsync_clk", .clk_mux = &disp_cc, .mux = 0x16 },
246+
{ .name = "disp_cc_mdss_vsync_clk", .clk_mux = &disp_cc, .mux = 0xb },
247+
{ .name = "measure_only_disp_cc_sleep_clk", .clk_mux = &disp_cc, .mux = 0x1d },
248+
{ .name = "measure_only_disp_cc_xo_clk", .clk_mux = &disp_cc, .mux = 0x1e },
249249

250-
{ "gpu_cc_ahb_clk", &gpu_cc, 0x11 },
251-
{ "gpu_cc_cx_gfx3d_clk", &gpu_cc, 0x1a },
252-
{ "gpu_cc_cx_gfx3d_slv_clk", &gpu_cc, 0x1b },
253-
{ "gpu_cc_cx_gmu_clk", &gpu_cc, 0x19 },
254-
{ "gpu_cc_cx_snoc_dvm_clk", &gpu_cc, 0x16 },
255-
{ "gpu_cc_cxo_aon_clk", &gpu_cc, 0xb },
256-
{ "gpu_cc_cxo_clk", &gpu_cc, 0xa },
257-
{ "gpu_cc_gx_cxo_clk", &gpu_cc, 0xf },
258-
{ "gpu_cc_gx_gfx3d_clk", &gpu_cc, 0xc },
259-
{ "gpu_cc_gx_gmu_clk", &gpu_cc, 0x10 },
260-
{ "gpu_cc_sleep_clk", &gpu_cc, 0x17 },
250+
{ .name = "gpu_cc_ahb_clk", .clk_mux = &gpu_cc, .mux = 0x11 },
251+
{ .name = "gpu_cc_cx_gfx3d_clk", .clk_mux = &gpu_cc, .mux = 0x1a },
252+
{ .name = "gpu_cc_cx_gfx3d_slv_clk", .clk_mux = &gpu_cc, .mux = 0x1b },
253+
{ .name = "gpu_cc_cx_gmu_clk", .clk_mux = &gpu_cc, .mux = 0x19 },
254+
{ .name = "gpu_cc_cx_snoc_dvm_clk", .clk_mux = &gpu_cc, .mux = 0x16 },
255+
{ .name = "gpu_cc_cxo_aon_clk", .clk_mux = &gpu_cc, .mux = 0xb },
256+
{ .name = "gpu_cc_cxo_clk", .clk_mux = &gpu_cc, .mux = 0xa },
257+
{ .name = "gpu_cc_gx_cxo_clk", .clk_mux = &gpu_cc, .mux = 0xf },
258+
{ .name = "gpu_cc_gx_gfx3d_clk", .clk_mux = &gpu_cc, .mux = 0xc },
259+
{ .name = "gpu_cc_gx_gmu_clk", .clk_mux = &gpu_cc, .mux = 0x10 },
260+
{ .name = "gpu_cc_sleep_clk", .clk_mux = &gpu_cc, .mux = 0x17 },
261261

262-
{ "mccc_clk", &mc_cc, 0x220 },
262+
{ .name = "mccc_clk", .clk_mux = &mc_cc, .mux = 0x220 },
263263
{}
264264
};
265265

266266
struct debugcc_platform sm6375_debugcc = {
267-
"sm6375",
268-
sm6375_clocks,
267+
.name = "sm6375",
268+
.clocks = sm6375_clocks,
269269
};

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