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[RISCV] Fix incorrect predicates for fp16 permutation intrinsics (#144063)
vrgatherei16, vslideup and vslidedown should be supported with fp16 type for Zvfhmin. Fixes #143975.
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18 files changed

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‎clang/include/clang/Basic/riscv_vector.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2397,7 +2397,7 @@ let RequiredFeatures = ["zvfbfmin"] in {
23972397
}
23982398
defm vrgatherei16 : RVVOutBuiltinSet<"vrgatherei16_vv", "csilfd",
23992399
[["vv", "v", "vv(Log2EEW:4)Uv"]]>;
2400-
let RequiredFeatures = ["zvfh"] in
2400+
let RequiredFeatures = ["zvfhmin"] in
24012401
defm vrgatherei16 : RVVOutBuiltinSet<"vrgatherei16_vv", "x",
24022402
[["vv", "v", "vv(Log2EEW:4)Uv"]]>;
24032403
// unsigned type

‎clang/include/clang/Basic/riscv_vector_common.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -593,7 +593,7 @@ let UnMaskedPolicyScheme = HasPolicyOperand,
593593
multiclass RVVSlideUpBuiltinSet {
594594
defm "" : RVVOutBuiltinSet<NAME, "csilfd",
595595
[["vx","v", "vvvz"]]>;
596-
let RequiredFeatures = ["zvfh"] in
596+
let RequiredFeatures = ["zvfhmin"] in
597597
defm "" : RVVOutBuiltinSet<NAME, "x",
598598
[["vx","v", "vvvz"]]>;
599599
defm "" : RVVOutBuiltinSet<NAME, "csil",
@@ -618,7 +618,7 @@ let UnMaskedPolicyScheme = HasPassthruOperand,
618618
multiclass RVVSlideDownBuiltinSet {
619619
defm "" : RVVOutBuiltinSet<NAME, "csilfd",
620620
[["vx","v", "vvz"]]>;
621-
let RequiredFeatures = ["zvfh"] in
621+
let RequiredFeatures = ["zvfhmin"] in
622622
defm "" : RVVOutBuiltinSet<NAME, "x",
623623
[["vx","v", "vvz"]]>;
624624
defm "" : RVVOutBuiltinSet<NAME, "csil",

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfhmin -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfhmin -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfhmin -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfhmin -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfhmin -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfhmin -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfhmin -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfhmin -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfhmin -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfhmin -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfhmin -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfhmin -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Lines changed: 10 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -7414,8 +7414,12 @@ defm : VPatTernaryV_VX_VI<"int_riscv_vslidedown", "PseudoVSLIDEDOWN", AllInteger
74147414
defm : VPatBinaryV_VX<"int_riscv_vslide1up", "PseudoVSLIDE1UP", AllIntegerVectors>;
74157415
defm : VPatBinaryV_VX<"int_riscv_vslide1down", "PseudoVSLIDE1DOWN", AllIntegerVectors>;
74167416

7417-
defm : VPatTernaryV_VX_VI<"int_riscv_vslideup", "PseudoVSLIDEUP", AllFloatVectors, uimm5>;
7418-
defm : VPatTernaryV_VX_VI<"int_riscv_vslidedown", "PseudoVSLIDEDOWN", AllFloatVectors, uimm5>;
7417+
defm : VPatTernaryV_VX_VI<"int_riscv_vslideup", "PseudoVSLIDEUP", AllFloatVectorsExceptFP16, uimm5>;
7418+
let Predicates = [HasVInstructionsF16Minimal] in
7419+
defm : VPatTernaryV_VX_VI<"int_riscv_vslideup", "PseudoVSLIDEUP", AllFP16Vectors, uimm5>;
7420+
defm : VPatTernaryV_VX_VI<"int_riscv_vslidedown", "PseudoVSLIDEDOWN", AllFloatVectorsExceptFP16, uimm5>;
7421+
let Predicates = [HasVInstructionsF16Minimal] in
7422+
defm : VPatTernaryV_VX_VI<"int_riscv_vslidedown", "PseudoVSLIDEDOWN", AllFP16Vectors, uimm5>;
74197423
defm : VPatBinaryV_VX<"int_riscv_vfslide1up", "PseudoVFSLIDE1UP", AllFloatVectors>;
74207424
defm : VPatBinaryV_VX<"int_riscv_vfslide1down", "PseudoVFSLIDE1DOWN", AllFloatVectors>;
74217425

@@ -7432,7 +7436,10 @@ defm : VPatBinaryV_VV_VX_VI_INT<"int_riscv_vrgather", "PseudoVRGATHER",
74327436
defm : VPatBinaryV_VV_VX_VI_INT<"int_riscv_vrgather", "PseudoVRGATHER",
74337437
AllBFloatVectors, uimm5>;
74347438
defm : VPatBinaryV_VV_INT_EEW<"int_riscv_vrgatherei16_vv", "PseudoVRGATHEREI16",
7435-
eew=16, vtilist=AllFloatVectors>;
7439+
eew=16, vtilist=AllFloatVectorsExceptFP16>;
7440+
let Predicates = [HasVInstructionsF16Minimal] in
7441+
defm : VPatBinaryV_VV_INT_EEW<"int_riscv_vrgatherei16_vv", "PseudoVRGATHEREI16",
7442+
eew=16, vtilist=AllFP16Vectors>;
74367443
//===----------------------------------------------------------------------===//
74377444
// 16.5. Vector Compress Instruction
74387445
//===----------------------------------------------------------------------===//

‎llvm/test/CodeGen/RISCV/rvv/vrgatherei16.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+d,+zvfh \
2+
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+d,+zvfhmin \
33
; RUN: -verify-machineinstrs | FileCheck %s
4-
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+d,+zvfh \
4+
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+d,+zvfhmin \
55
; RUN: -verify-machineinstrs | FileCheck %s
66

77
declare <vscale x 1 x i8> @llvm.riscv.vrgatherei16.vv.nxv1i8(

‎llvm/test/CodeGen/RISCV/rvv/vslidedown.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+d,+zvfh \
2+
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+d,+zvfhmin \
33
; RUN: -verify-machineinstrs | FileCheck %s
4-
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+d,+zvfh \
4+
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+d,+zvfhmin \
55
; RUN: -verify-machineinstrs | FileCheck %s
66

77
declare <vscale x 1 x i8> @llvm.riscv.vslidedown.nxv1i8(

‎llvm/test/CodeGen/RISCV/rvv/vslideup.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+d,+zvfh \
2+
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+d,+zvfhmin \
33
; RUN: -verify-machineinstrs | FileCheck %s
4-
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+d,+zvfh \
4+
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+d,+zvfhmin \
55
; RUN: -verify-machineinstrs | FileCheck %s
66

77
declare <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8(

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