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NRFX-7253: Various adaptations needed for nrf92 IRONSide
Signed-off-by: Aymen Laouini <[email protected]>
1 parent 893c333 commit 8992728

18 files changed

+369
-9
lines changed

‎boards/nordic/nrf9280pdk/Kconfig.defconfig

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@@ -19,3 +19,13 @@ config ASSERT
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default n if ZTEST
2020

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endif # BOARD_NRF9280PDK_NRF9280_CPUPPR
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if BOARD_NRF9280PDK_NRF9280_CPUAPP_IRON
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config ROM_START_OFFSET
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default 0x800 if BOOTLOADER_MCUBOOT
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config FLASH_LOAD_OFFSET
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default 0x2c000 if !USE_DT_CODE_PARTITION
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endif # BOARD_NRF9280PDK_NRF9280_CPUAPP_IRON

‎boards/nordic/nrf9280pdk/Kconfig.nrf9280pdk

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@@ -2,7 +2,9 @@
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_NRF9280PDK
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select SOC_NRF9280_CPUAPP if BOARD_NRF9280PDK_NRF9280_CPUAPP
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select SOC_NRF9280_CPUAPP if (BOARD_NRF9280PDK_NRF9280_CPUAPP || \
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BOARD_NRF9280PDK_NRF9280_CPUAPP_IRON)
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select SOC_NRF9280_CPURAD if BOARD_NRF9280PDK_NRF9280_CPURAD
7-
select SOC_NRF9280_CPUPPR if BOARD_NRF9280PDK_NRF9280_CPUPPR || \
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BOARD_NRF9280PDK_NRF9280_CPUPPR_XIP
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select SOC_NRF9280_CPUPPR if (BOARD_NRF9280PDK_NRF9280_CPUPPR || \
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BOARD_NRF9280PDK_NRF9280_CPUPPR_XIP)
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select SOC_NRF9280_IRON if BOARD_NRF9280PDK_NRF9280_CPUAPP_IRON

‎boards/nordic/nrf9280pdk/board.yml

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@@ -7,3 +7,5 @@ board:
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variants:
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- name: xip
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cpucluster: cpuppr
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- name: iron
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cpucluster: cpuapp

‎boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-ipc_conf_iron.dtsi

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/*
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* Copyright (c) 2025 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* This file is to be merged with the original ipc_conf.dtsi in the future. */
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/ {
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ipc {
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/delete-node/ ipc-1-2;
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/delete-node/ ipc-1-3;
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cpusec_cpuapp_ipc: ipc-1-2 {
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compatible = "nordic,ironside-call";
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memory-region = <&cpusec_cpuapp_ipc_shm>;
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mboxes = <&cpusec_bellboard 12>,
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<&cpuapp_bellboard 0>;
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status = "disabled";
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};
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cpusec_cpurad_ipc: ipc-1-3 {
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compatible = "nordic,ironside-call";
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memory-region = <&cpusec_cpurad_ipc_shm>;
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mboxes = <&cpusec_bellboard 18>,
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<&cpurad_bellboard 0>;
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status = "disabled";
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};
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};
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};

‎boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-memory_map.dtsi

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@@ -197,8 +197,8 @@
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#address-cells = <1>;
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#size-cells = <1>;
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200-
cpuapp_slot0_partition: partition@442000 {
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reg = <0x442000 DT_SIZE_K(1024)>;
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cpuapp_slot0_partition: partition@33000 {
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reg = <0x33000 DT_SIZE_K(1024)>;
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};
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cpuppr_code_partition: partition@542000 {

‎boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-memory_map_iron.dtsi

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/*
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* Copyright (c) 2025 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* This file is to be merged with the original memory_map.dtsi in the future.
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* The following nodes will be replaced:
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*/
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/delete-node/ &cpuapp_cpusec_ipc_shm;
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/delete-node/ &cpuapp_cpusys_ipc_shm;
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/delete-node/ &cpurad_cpusec_ipc_shm;
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/delete-node/ &cpurad_cpusys_ipc_shm;
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/delete-node/ &cpusec_cpuapp_ipc_shm;
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/delete-node/ &cpusec_cpurad_ipc_shm;
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/delete-node/ &cpusys_cpuapp_ipc_shm;
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/delete-node/ &cpusys_cpurad_ipc_shm;
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/delete-node/ &cpuapp_rw_partitions;
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/delete-node/ &cpuapp_rx_partitions;
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/delete-node/ &cpurad_rx_partitions;
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/ {
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reserved-memory {
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cpuapp_cpusys_ipc_shm: memory@2f88fce0 {
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reg = <0x2f88fce0 0x80>;
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};
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cpusys_cpuapp_ipc_shm: memory@2f88fd60 {
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reg = <0x2f88fd60 0x80>;
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};
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cpurad_cpusys_ipc_shm: memory@2f88fe00 {
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reg = <0x2f88fe00 0x80>;
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};
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cpusys_cpurad_ipc_shm: memory@2f88fe80 {
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reg = <0x2f88fe80 0x80>;
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};
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cpusec_cpurad_ipc_shm: memory@2f88f800 {
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reg = <0x2f88f800 0x80>;
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};
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cpurad_ironside_se_event_report: memory@2f88f880 {
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reg = <0x2f88f880 0x100>;
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};
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cpurad_ironside_se_boot_report: memory@2f88f980 {
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reg = <0x2f88f980 0x200>;
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};
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cpusec_cpuapp_ipc_shm: memory@2f88fb80 {
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reg = <0x2f88fb80 0x80>;
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};
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cpuapp_ironside_se_event_report: memory@2f88fc00 {
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reg = <0x2f88fc00 0x100>;
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};
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cpuapp_ironside_se_boot_report: memory@2f88fd00 {
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reg = <0x2f88fd00 0x200>;
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};
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};
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};
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&mram1x {
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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cpuapp_boot_partition: partition@2c000 {
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reg = <0x2c000 DT_SIZE_K(64)>;
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};
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cpuapp_slot0_partition: partition@3c000 {
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reg = <0x3c000 DT_SIZE_K(336)>;
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};
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cpurad_slot0_partition: partition@90000 {
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reg = <0x90000 DT_SIZE_K(336)>;
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};
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cpuppr_code_partition: partition@e4000 {
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reg = <0xe4000 DT_SIZE_K(64)>;
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};
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cpuflpr_code_partition: partition@f4000 {
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reg = <0xf4000 DT_SIZE_K(48)>;
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};
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cpuapp_slot1_partition: partition@100000 {
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reg = <0x100000 DT_SIZE_K(336)>;
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};
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cpurad_slot1_partition: partition@154000 {
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reg = <0x154000 DT_SIZE_K(336)>;
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};
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storage_partition: partition@1a8000 {
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reg = <0x1a8000 DT_SIZE_K(40)>;
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};
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};
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};

‎boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp_iron.dts

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/*
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* Copyright (c) 2025 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "nrf9280pdk_nrf9280_cpuapp.dts"
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#include "nrf9280pdk_nrf9280-ipc_conf_iron.dtsi"
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#include "nrf9280pdk_nrf9280-memory_map_iron.dtsi"
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/delete-node/ &cpusec_cpurad_ipc;
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/ {
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chosen {
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zephyr,code-partition = &slot0_partition;
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zephyr,uart-mcumgr = &uart136;
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};
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};
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&cpusec_bellboard {
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status = "okay";
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};
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&cpusec_cpuapp_ipc {
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mbox-names = "tx", "rx";
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status = "okay";
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};
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boot_partition: &cpuapp_boot_partition {
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label = "mcuboot";
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};
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slot0_partition: &cpuapp_slot0_partition {
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label = "image-0";
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};
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slot1_partition: &cpuapp_slot1_partition {
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label = "image-1";
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};

‎boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp_iron.yaml

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# Copyright (c) 2024 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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identifier: nrf9280pdk/nrf9280/cpuapp
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name: nRF9280-DK-nRF9280-Application
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type: mcu
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arch: arm
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toolchain:
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- gnuarmemb
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- xtools
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- zephyr
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sysbuild: true
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ram: 512
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flash: 1024
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supported:
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- adc
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- counter
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- gpio
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- i2c
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- pwm
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- spi
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- watchdog
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- usbd

‎boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp_iron_defconfig

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# Copyright (c) 2024 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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# Enable UART driver
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CONFIG_SERIAL=y
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# Enable console
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CONFIG_CONSOLE=y
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CONFIG_UART_CONSOLE=y
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# Enable MPU
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CONFIG_ARM_MPU=y
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# Enable hardware stack protection
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CONFIG_HW_STACK_PROTECTION=y
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# MPU-based null-pointer dereferencing detection cannot be applied
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# as the (0x0 - 0x400) region is unmapped for this target.
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CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
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# Enable cache
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CONFIG_CACHE_MANAGEMENT=y
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CONFIG_EXTERNAL_CACHE=y
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# Enable GPIO
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CONFIG_GPIO=y
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# UICR generation is not supported, and when reintroduced will not use nrf-regtool.
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CONFIG_NRF_REGTOOL_GENERATE_UICR=n

‎drivers/firmware/nrf_ironside/Kconfig

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@@ -3,7 +3,7 @@
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44
config NRF_IRONSIDE
55
bool
6-
depends on SOC_NRF54H20_IRON
6+
depends on SOC_NRF54H20_IRON || SOC_NRF9280_IRON
77
help
88
This is selected by drivers interacting with Nordic IRONside firmware.
99

@@ -28,11 +28,11 @@ config NRF_IRONSIDE_CALL_INIT_PRIORITY
2828
endif # NRF_IRONSIDE_CALL
2929

3030
menu "Nordic IRONside services"
31-
depends on SOC_NRF54H20_IRON
31+
depends on SOC_NRF54H20_IRON || SOC_NRF9280_IRON
3232

3333
config NRF_IRONSIDE_CPUCONF_SERVICE
3434
bool "IRONside CPUCONF service"
35-
depends on SOC_NRF54H20_CPUAPP
35+
depends on SOC_NRF54H20_CPUAPP || SOC_NRF9280_CPUAPP
3636
select NRF_IRONSIDE_CALL
3737
help
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Service used to boot local domain cores.

‎samples/drivers/firmware/nrf_ironside/update/sample.yaml

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@@ -6,7 +6,10 @@ common:
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tags: nrf_ironside
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integration_platforms:
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- nrf54h20dk/nrf54h20/cpuapp/iron
9+
- nrf9280pdk/nrf9280/cpuapp/iron
910

1011
tests:
1112
sample.drivers.firmware.nrf_ironside.update:
12-
platform_allow: nrf54h20dk/nrf54h20/cpuapp/iron
13+
platform_allow:
14+
- nrf54h20dk/nrf54h20/cpuapp/iron
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- nrf9280pdk/nrf9280/cpuapp/iron

‎soc/nordic/nrf92/CMakeLists.txt

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@@ -10,3 +10,5 @@ zephyr_include_directories(.)
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# Ensure that image size aligns with 16 bytes so that MRAMC finalizes all writes
1111
# for the image correctly
1212
zephyr_linker_sources(SECTIONS SORT_KEY zzz_place_align_at_end align.ld)
13+
14+
add_subdirectory(ironside/se)

‎soc/nordic/nrf92/Kconfig

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@@ -48,3 +48,6 @@ config SOC_NRF9230_ENGB_CPURAD
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4949
config SOC_NRF9230_ENGB_CPUPPR
5050
select RISCV_CORE_NORDIC_VPR
51+
52+
config SOC_NRF9280_IRON
53+
select EXPERIMENTAL if MCUBOOT

‎soc/nordic/nrf92/Kconfig.soc

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@@ -62,5 +62,10 @@ config SOC_NRF9280_CPUPPR
6262
help
6363
nRF9280 CPUPPR
6464

65+
config SOC_NRF9280_IRON
66+
bool
67+
help
68+
Indicates that local domain firmware is compatible with Nordic IRONside SE.
69+
6570
config SOC
6671
default "nrf9280" if SOC_NRF9280

‎soc/nordic/nrf92/ironside/se/CMakeLists.txt

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# Copyright (c) 2025 Nordic Semiconductor
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# SPDX-License-Identifier: Apache-2.0
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4+
zephyr_library_sources_ifdef(CONFIG_SOC_NRF54H20_IRONSIDE_SE_BOOT_REPORT ironside_se_boot_report.c)
5+
zephyr_include_directories(include)

‎soc/nordic/nrf92/ironside/se/Kconfig

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# Copyright (c) 2025 Nordic Semiconductor
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# SPDX-License-Identifier: Apache-2.0
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4+
config SOC_NRF9280_IRONSIDE_SE_BOOT_REPORT
5+
bool "Nordic IRONside SE boot report"
6+
default y if SOC_NRF9280_CPUAPP || SOC_NRF9251_CPUAPP
7+
depends on SOC_NRF9280_IRON
8+
help
9+
This option enables parsing of the Boot Report populated by Nordic IRONside SE.
10+
11+
config SOC_NRF9280_IRONSIDE_SE_BOOT_REPORT_MAGIC
12+
hex
13+
default 0x4d69546f
14+
help
15+
Constant used to check if an Nordic IRONside SE boot report has been written.

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