Rework PCI emulation to better expose inner data

The previous structure for PCI device emulation made it inconvenient to
access the inner data of devices for initialization during setup.  This
attempts to flatten some of the data model at the cost of more
monoporphization.

Author: pfmooney

propolis/src/block/file.rs

@@ -105,6 +105,7 @@ impl Driver {
         })
     }
     fn blocking_loop(&self, sctx: &mut SyncCtx) {
+        let mut idled = false;
         loop {
             if sctx.check_yield() {
                 break;
@@ -113,14 +114,18 @@ impl Driver {
             let mut guard = self.queue.lock().unwrap();
             if let Some(req) = guard.pop_front() {
                 drop(guard);
+                idled = false;
                 let ctx = sctx.dispctx();
                 match process_request(&self.fp, &req, &ctx) {
                     Ok(_) => req.complete(block::Result::Success, &ctx),
                     Err(_) => req.complete(block::Result::Failure, &ctx),
                 }
             } else {
                 // wait until more requests are available
-                self.idle_threads.add_permits(1);
+                if !idled {
+                    self.idle_threads.add_permits(1);
+                    idled = true;
+                }
                 let _guard = self
                     .cv
                     .wait_while(guard, |g| {