Add support for Arm Neoverse V2 (#194)

Author: paolotricerri

README.md

@@ -272,7 +272,7 @@ LDFLAGS+= $(pkg-config --libs libcpuinfo)
   - [x] AMD-designed x86/x86-64 cores (up to Puma/Jaguar and Zen 2)
   - [ ] VIA-designed x86/x86-64 cores
   - [ ] Other x86 cores (DM&P, RDC, Transmeta, Cyrix, Rise)
-  - [x] ARM-designed ARM cores (up to Cortex-A55, Cortex-A77, and Neoverse E1/V1/N2)
+  - [x] ARM-designed ARM cores (up to Cortex-A55, Cortex-A77, and Neoverse E1/V1/N2/V2)
   - [x] Qualcomm-designed ARM cores (Scorpion, Krait, and Kryo)
   - [x] Nvidia-designed ARM cores (Denver and Carmel)
   - [x] Samsung-designed ARM cores (Exynos)

include/cpuinfo.h

@@ -432,6 +432,8 @@ enum cpuinfo_uarch {
 	cpuinfo_uarch_neoverse_v1  = 0x00300402,
 	/** ARM Neoverse N2. */
 	cpuinfo_uarch_neoverse_n2  = 0x00300403,
+	/** ARM Neoverse V2. */
+	cpuinfo_uarch_neoverse_v2  = 0x00300404,
 
 	/** ARM Cortex-X1. */
 	cpuinfo_uarch_cortex_x1    = 0x00300501,

src/arm/cache.c

@@ -1241,35 +1241,29 @@ void cpuinfo_arm_decode_cache(
 		case cpuinfo_uarch_neoverse_n1:
 		case cpuinfo_uarch_neoverse_v1:
 		case cpuinfo_uarch_neoverse_n2:
+		case cpuinfo_uarch_neoverse_v2:
 		{
-                        /*
-                         * ARM Neoverse-n1 Core Technical Reference Manual
-                         * A6.1. About the L1 memory system
-			 *   The L1 memory system consists of separate instruction and data caches. Both have a fixed size of 64KB.
-                         *
-                         * A6.1.1 L1 instruction-side memory system
-                         *   The L1 instruction memory system has the following key features:
-                         *    - Virtually Indexed, Physically Tagged (VIPT), which behaves as a Physically Indexed,
-                         *      Physically Tagged (PIPT) 4-way set-associative L1 data cache.
-                         *    - Fixed cache line length of 64 bytes.
-                         *
-                         * A6.1.2 L1 data-side memory system
-                         *   The L1 data memory system has the following features:
-                         *    - Virtually Indexed, Physically Tagged (VIPT), which behaves as a Physically Indexed,
-                         *      Physically Tagged (PIPT) 4-way set-associative L1 data cache.
-                         *    - Fixed cache line length of 64 bytes.
-                         *    - Pseudo-LRU cache replacement policy.
-                         *
-                         * A7.1 About the L2 memory system
-                         *   The L2 memory subsystem consist of:
-			 *    - An 8-way set associative L2 cache with a configurable size of 256KB, 512KB, or 1024KB. Cache lines
-			 *      have a fixed length of 64 bytes.
-                         *    - Strictly inclusive with L1 data cache.
-			 *    - When configured with instruction cache hardware coherency, strictly inclusive with L1 instruction cache.
-			 *    - When configured without instruction cache hardware coherency, weakly inclusive with L1 instruction cache.
-                         */
-
-			const uint32_t min_l2_size_KB= 256;
+			/*
+				* The specifications here below are taken from the
+				* Arm Core Technical Reference Manuals for
+                                *  - Neoverse N1: https://developer.arm.com/documentation/100616/0401/?lang=en
+                                *  - Neoverse N2: https://developer.arm.com/documentation/102099/0003/?lang=en
+                                *  - Neoverse V1: https://developer.arm.com/documentation/101427/0102/?lang=en
+                                *  - Neoverse V2: https://developer.arm.com/documentation/102375/0002/?lang=en
+				*
+                                * All four Arm architectures have L1 memory system with instruction and data caches,
+                                * both of fixed size of 64KB. The instruction side memory system is 4-way set associative
+                                * with a cache line length of 64 bytes. The data cache is also 4-way set associative with
+                                * a cache line length of 64 bytes.
+				*
+                                * The L2 memory system differs across the four Architectures in the minimum
+                                * length of the L2 cache. Namely:
+                                *  - Arm Neoverse N1/N2/V1 have a L2 cache of configurable size of 256KB, 512KB, or 1024KB
+                                *  - Arm Neoverse V2 has a L2 cache of configurable size of 1MB or 2MB
+                                * For all four architectures, the L2 cache is 8-way set associative
+                                * For all other information, please refer to the technical manuals linked above
+			*/
+			const uint32_t min_l2_size_KB = uarch == cpuinfo_uarch_neoverse_v2 ? 1024 : 256;
 			const uint32_t min_l3_size_KB = 0;
 
 			*l1i = (struct cpuinfo_cache) {
@@ -1715,6 +1709,7 @@ uint32_t cpuinfo_arm_compute_max_cache_size(const struct cpuinfo_processor* proc
 		case cpuinfo_uarch_neoverse_n1:
 		case cpuinfo_uarch_neoverse_v1:
 		case cpuinfo_uarch_neoverse_n2:
+		case cpuinfo_uarch_neoverse_v2:
 		case cpuinfo_uarch_cortex_a75:
 		case cpuinfo_uarch_cortex_a76:
 		case cpuinfo_uarch_exynos_m4:

src/arm/linux/aarch32-isa.c

@@ -79,6 +79,7 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo(
 		 * - Neoverse N1 cores
 		 * - Neoverse N2 cores
 		 * - Neoverse V1 cores
+		 * - Neoverse V2 cores
 		 */
 		if (chipset->series == cpuinfo_arm_chipset_series_samsung_exynos && chipset->model == 9810) {
 			/* Only little cores of Exynos 9810 support FP16 & RDM */
@@ -100,6 +101,7 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo(
 				case UINT32_C(0x4100D490): /* Neoverse N2 */
 				case UINT32_C(0x4100D4D0): /* Cortex-A715 */
 				case UINT32_C(0x4100D4E0): /* Cortex-X3 */
+				case UINT32_C(0x4100D4F0): /* Neoverse V2 */
 				case UINT32_C(0x4800D400): /* Cortex-A76 (HiSilicon) */
 				case UINT32_C(0x51008020): /* Kryo 385 Gold (Cortex-A75) */
 				case UINT32_C(0x51008030): /* Kryo 385 Silver (Cortex-A55) */
@@ -130,6 +132,7 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo(
 		 * - Neoverse N1 cores
 		 * - Neoverse N2 cores
 		 * - Neoverse V1 cores
+		 * - Neoverse V2 cores
 		 */
 		if (chipset->series == cpuinfo_arm_chipset_series_spreadtrum_sc && chipset->model == 9863) {
 			cpuinfo_log_warning("VDOT instructions disabled: cause occasional SIGILL on Spreadtrum SC9863A");
@@ -150,6 +153,7 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo(
 				case UINT32_C(0x4100D490): /* Neoverse N2 */
 				case UINT32_C(0x4100D4D0): /* Cortex-A715 */
 				case UINT32_C(0x4100D4E0): /* Cortex-X3 */
+				case UINT32_C(0x4100D4F0): /* Neoverse V2 */
 				case UINT32_C(0x4800D400): /* Cortex-A76 (HiSilicon) */
 				case UINT32_C(0x51008040): /* Kryo 485 Gold (Cortex-A76) */
 				case UINT32_C(0x51008050): /* Kryo 485 Silver (Cortex-A55) */

src/arm/linux/aarch64-isa.c

@@ -43,6 +43,7 @@ void cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo(
 	 * - Neoverse N1 cores
 	 * - Neoverse V1 cores
 	 * - Neoverse N2 cores
+	 * - Neoverse V2 cores
 	 */
 	if (chipset->series == cpuinfo_arm_chipset_series_samsung_exynos && chipset->model == 9810) {
 		/* Exynos 9810 reports that it supports FP16 compute, but in fact only little cores do */
@@ -59,6 +60,7 @@ void cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo(
 			case UINT32_C(0x4100D0E0): /* Cortex-A76AE */
 			case UINT32_C(0x4100D400): /* Neoverse V1 */
 			case UINT32_C(0x4100D490): /* Neoverse N2 */
+			case UINT32_C(0x4100D4F0): /* Neoverse V2 */
 			case UINT32_C(0x4800D400): /* Cortex-A76 (HiSilicon) */
 			case UINT32_C(0x51008020): /* Kryo 385 Gold (Cortex-A75) */
 			case UINT32_C(0x51008030): /* Kryo 385 Silver (Cortex-A55) */
@@ -100,6 +102,7 @@ void cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo(
 		case UINT32_C(0x4100D400): /* Neoverse V1 */
 		case UINT32_C(0x4100D490): /* Neoverse N2 */
 		case UINT32_C(0x4100D4A0): /* Neoverse E1 */
+		case UINT32_C(0x4100D4F0): /* Neoverse V2 */
 		case UINT32_C(0x4800D400): /* Cortex-A76 (HiSilicon) */
 		case UINT32_C(0x51008040): /* Kryo 485 Gold (Cortex-A76) */
 		case UINT32_C(0x51008050): /* Kryo 485 Silver (Cortex-A55) */

src/arm/uarch.c

@@ -89,7 +89,7 @@ void cpuinfo_arm_decode_vendor_uarch(
 				case 0xD0E: /* Cortex-A76AE */
 					*uarch = cpuinfo_uarch_cortex_a76;
 					break;
-				case 0xD40:
+				case 0xD40: /* Neoverse V1 */
 					*uarch = cpuinfo_uarch_neoverse_v1;
 					break;
 				case 0xD41: /* Cortex-A78 */
@@ -107,7 +107,7 @@ void cpuinfo_arm_decode_vendor_uarch(
 				case 0xD48: /* Cortex-X2 */
 					*uarch = cpuinfo_uarch_cortex_x2;
 					break;
-				case 0xD49:
+				case 0xD49: /* Neoverse N2 */
 					*uarch = cpuinfo_uarch_neoverse_n2;
 					break;
 #if CPUINFO_ARCH_ARM64
@@ -121,6 +121,9 @@ void cpuinfo_arm_decode_vendor_uarch(
 				case 0xD4E: /* Cortex-X3 */
 					*uarch = cpuinfo_uarch_cortex_x3;
 					break;
+				case 0xD4F: /* Neoverse V2 */
+					*uarch = cpuinfo_uarch_neoverse_v2;
+					break;
 				default:
 					switch (midr_get_part(midr) >> 8) {
 #if CPUINFO_ARCH_ARM

tools/cpu-info.c

@@ -209,6 +209,8 @@ static const char* uarch_to_string(enum cpuinfo_uarch uarch) {
 			return "Neoverse V1";
 		case cpuinfo_uarch_neoverse_n2:
 			return "Neoverse N2";
+		case cpuinfo_uarch_neoverse_v2:
+			return "Neoverse V2";
 		case cpuinfo_uarch_scorpion:
 			return "Scorpion";
 		case cpuinfo_uarch_krait: