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reverse to servo enable
1 parent 22b600b commit b608ecf

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+3
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phaser.py

+3-4
Original file line numberDiff line numberDiff line change
@@ -281,7 +281,7 @@ def __init__(self, platform):
281281
self.sync += [
282282
If(
283283
iir.stb_out,
284-
# bit 0 is the ch bypass bit, bit 1 the hold bit
284+
# bit 0 is the ch enable bit, bit 1 the hold bit
285285
iir.ch_profile[0].eq(self.decoder.get(f"servo0_cfg", "write")[2:]),
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iir.ch_profile[1].eq(self.decoder.get(f"servo1_cfg", "write")[2:]),
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iir.hold[0].eq(self.decoder.get(f"servo0_cfg", "write")[1]),
@@ -301,8 +301,7 @@ def __init__(self, platform):
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duc = PhasedDUC(n=2, pwidth=19, fwidth=32, zl=10)
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self.submodules += duc
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cfg = self.decoder.get("duc{}_cfg".format(ch), "write")
304-
# negated servo bypass
305-
n_servo_bypass = self.decoder.get("servo{}_cfg".format(ch), "write")[0]
304+
servo_enable = self.decoder.get("servo{}_cfg".format(ch), "write")[0]
306305
self.sync += [
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# keep accu cleared
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duc.clr.eq(cfg[0]),
@@ -341,7 +340,7 @@ def __init__(self, platform):
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servo_dsp_i.b.eq(iir.outp[ch]),
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servo_dsp_q.b.eq(iir.outp[ch]),
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If(
344-
n_servo_bypass,
343+
servo_enable,
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self.dac.data[2 * t][ch].eq(
346345
servo_dsp_i.p >> len(self.dac.data[2 * t][ch] - 1)
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),

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