@@ -281,7 +281,7 @@ def __init__(self, platform):
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self .sync += [
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If (
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iir .stb_out ,
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- # bit 0 is the ch bypass bit, bit 1 the hold bit
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+ # bit 0 is the ch enable bit, bit 1 the hold bit
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iir .ch_profile [0 ].eq (self .decoder .get (f"servo0_cfg" , "write" )[2 :]),
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iir .ch_profile [1 ].eq (self .decoder .get (f"servo1_cfg" , "write" )[2 :]),
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iir .hold [0 ].eq (self .decoder .get (f"servo0_cfg" , "write" )[1 ]),
@@ -301,8 +301,7 @@ def __init__(self, platform):
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duc = PhasedDUC (n = 2 , pwidth = 19 , fwidth = 32 , zl = 10 )
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self .submodules += duc
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cfg = self .decoder .get ("duc{}_cfg" .format (ch ), "write" )
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- # negated servo bypass
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- n_servo_bypass = self .decoder .get ("servo{}_cfg" .format (ch ), "write" )[0 ]
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+ servo_enable = self .decoder .get ("servo{}_cfg" .format (ch ), "write" )[0 ]
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self .sync += [
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# keep accu cleared
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duc .clr .eq (cfg [0 ]),
@@ -341,7 +340,7 @@ def __init__(self, platform):
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servo_dsp_i .b .eq (iir .outp [ch ]),
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servo_dsp_q .b .eq (iir .outp [ch ]),
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If (
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- n_servo_bypass ,
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+ servo_enable ,
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self .dac .data [2 * t ][ch ].eq (
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servo_dsp_i .p >> len (self .dac .data [2 * t ][ch ] - 1 )
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),
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