target/riscv: active dm before get nextdm

when Debug Module is inactive, accesses to the nextdm may fail.
Specifically, nextdm might not return correct data.

Author: lz-bro

src/target/riscv/riscv-013.c

@@ -538,12 +538,39 @@ static bool check_dbgbase_exists(struct target *target)
 {
 	uint32_t next_dm = 0;
 	unsigned int count = 1;
+	uint32_t dmcontrol = 0;
 
 	LOG_TARGET_DEBUG(target, "Searching for DM with DMI base address (dbgbase) = 0x%x", target->dbgbase);
 	while (1) {
 		uint32_t current_dm = next_dm;
 		if (current_dm == target->dbgbase)
 			return true;
+
+		if (dmi_read(target, &dmcontrol, DM_DMCONTROL + current_dm) != ERROR_OK)
+			break;
+		if (!get_field32(dmcontrol, DM_DMCONTROL_DMACTIVE)) {
+			LOG_TARGET_DEBUG(target, "Activating the DM with DMI base address (dbgbase) = 0x%x", current_dm);
+			if (dmi_write(target, DM_DMCONTROL + current_dm, DM_DMCONTROL_DMACTIVE) != ERROR_OK)
+				break;
+
+			const time_t start = time(NULL);
+			LOG_TARGET_DEBUG(target, "Waiting for the DM to become active.");
+			do {
+				if (dmi_read(target, &dmcontrol, DM_DMCONTROL + current_dm) != ERROR_OK)
+					return false;
+
+				if (time(NULL) - start > riscv_get_command_timeout_sec()) {
+					LOG_TARGET_ERROR(target, "Debug Module did not become active in %d s. "
+							"Increase the timeout with 'riscv set_command_timeout_sec'.",
+							riscv_get_command_timeout_sec());
+					return ERROR_TIMEOUT_REACHED;
+				}
+
+
+			} while (!get_field32(dmcontrol, DM_DMCONTROL_DMACTIVE));
+			LOG_TARGET_DEBUG(target, "DM is active.");
+		}
+
 		if (dmi_read(target, &next_dm, DM_NEXTDM + current_dm) != ERROR_OK)
 			break;
 		LOG_TARGET_DEBUG(target, "dm @ 0x%x --> nextdm=0x%x", current_dm, next_dm);