Initial commit.

Author: dvc94ch

.cargo/config

@@ -0,0 +1,7 @@
+[target.riscv32imac-unknown-none]
+runner = 'riscv32-unknown-elf-gdb'
+rustflags = [
+  "-C", "link-arg=-Tmemory.x",
+  "-C", "link-arg=-Tlink.x",
+  "-C", "linker=riscv32-unknown-elf-ld",
+]

.gdbinit

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+set remotetimeout 240
+target extended-remote localhost:3333
+
+define upload
+  monitor reset halt
+  monitor flash protect 0 64 last off
+  load
+  monitor flash protect 0 64 last on
+  continue
+end
+document upload
+Upload program to hifive board
+end
+
+# Load Rust's GDB pretty printers
+python
+import os;
+import sys;
+path = os.environ['TOOLCHAIN'] + '/lib/rustlib/etc'
+sys.path.append(path)
+
+gdb.execute('directory %s' % path)
+gdb.execute('add-auto-load-safe-path %s' % path)
+end

.gitignore

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+
+/target
+**/*.rs.bk

.gitmodules

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+[submodule "hifive"]
+	path = hifive
+	url = https://github.com/dvc94ch/hifive
+[submodule "riscv-rt"]
+	path = riscv-rt
+	url = https://github.com/dvc94ch/riscv-rt
+[submodule "riscv"]
+	path = riscv
+	url = https://github.com/dvc94ch/riscv
+[submodule "e310x"]
+	path = e310x
+	url = https://github.com/dvc94ch/e310x

Cargo.lock

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+[package]
+name = "riscv-crates"
+version = "0.1.0"
+authors = ["David Craven <[email protected]>"]
+
+[workspace]
+
+[dependencies]
+embedded-hal = { git = "https://github.com/japaric/embedded-hal", rev = "7d904f515d15fd5fe7ea34e18820ea83e2651fa2" }
+nb = { git = "https://github.com/japaric/nb" }
+hifive = { path = "hifive" }
+
+[profile.release]
+debug = true
+lto = true

Cargo.toml

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+# Examples (uncomment one)
+#EXAMPLE      := blinky_delay
+#EXAMPLE      := blinky_clint
+#EXAMPLE      := blinky_pwm
+#EXAMPLE      := blinky_plic
+#EXAMPLE      := hello_world
+#EXAMPLE      := panicking
+#EXAMPLE      := pll
+
+# Board crate (uncomment one)
+BOARD        := hifive
+
+TARGET       := riscv32imac-unknown-none
+TARGET_DIR   := $(abspath ./target/$(TARGET)/debug)
+EXAMPLE_DIR  := $(TARGET_DIR)/examples
+EXAMPLE_BIN  := $(EXAMPLE_DIR)/$(EXAMPLE)
+OPENOCD_CFG  := openocd.cfg
+
+build:
+	xargo build --examples --target $(TARGET) $(ARGS)
+
+test:
+	xargo test --all --target $(TARGET) $(ARGS)
+
+clean:
+	xargo clean $(ARGS)
+
+readelf:
+	llvm-readelf -a -h -s -r -symbols $(EXAMPLE_BIN) $(ARGS)
+
+objdump:
+	llvm-objdump -d -S $(EXAMPLE_BIN) $(ARGS)
+
+size:
+	llvm-size $(EXAMPLE_BIN) $(ARGS)
+
+# .gdbinit adds a upload command to gdb
+gdb:
+	riscv32-unknown-elf-gdb $(EXAMPLE_BIN) $(ARGS)
+
+openocd:
+	openocd -f $(OPENOCD_CFG) $(ARGS)
+
+upload:
+	openocd -f $(OPENOCD_CFG) \
+		-c "flash protect 0 64 last off; program ${EXAMPLE_BIN}; resume 0x20400000; exit"
+
+framedump:
+	riscv32-unknown-elf-readelf --debug-dump=frames $(EXAMPLE_BIN) $(ARGS)
+
+.PHONY: build clean readelf objdump framedump size gdb openocd spike

Makefile

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+[dependencies]
+core = {}
+alloc = {}
+
+[dependencies.compiler_builtins]
+features = ["mem"]
+stage = 1

Xargo.toml

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+export RISCV_RUST_TOOLCHAIN=~/repos/riscv-rust
+export TOOLCHAIN=$RISCV_RUST_TOOLCHAIN/toolchain
+
+export PATH=/opt/rust/bin:/opt/riscv/bin:~/.cargo/bin:$PATH
+export XARGO_RUST_SRC=~/repos/rust/src
+export RUST_TARGET_PATH=$PWD

e310x

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+#![no_std]
+
+extern crate hifive;
+
+use hifive::prelude::*;
+use hifive::{interrupt, led, Blue, Clint, Peripherals, UExt};
+
+fn main() {
+    let peripherals = hifive::init(115_200);
+    led::init(peripherals.GPIO0);
+
+    let timer = Clint(peripherals.CLINT);
+    timer.set_timeout(1.s());
+
+    unsafe {
+        interrupt::enable();
+    }
+}
+
+#[no_mangle]
+pub fn mtimer_trap_handler(p: &Peripherals) {
+    Clint(p.CLINT).restart();
+    Blue::toggle(p.GPIO0);
+}

env.sh

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+#![no_std]
+
+#[macro_use]
+extern crate nb;
+extern crate hifive;
+
+use hifive::prelude::*;
+use hifive::{led, Red, Green, Blue, Clint, UExt};
+
+fn delay(clint: &Clint) {
+    block!(clint.wait()).unwrap();
+    clint.restart();
+}
+
+fn main() {
+    let peripherals = hifive::init(115_200);
+    led::init(peripherals.GPIO0);
+
+    let clint = Clint(peripherals.CLINT);
+    clint.set_timeout(500.ms());
+
+    let gpio = peripherals.GPIO0;
+    loop {
+        Red::on(gpio);
+        delay(&clint);
+        Red::off(gpio);
+        Green::on(gpio);
+        delay(&clint);
+        Green::off(gpio);
+        Blue::on(gpio);
+        delay(&clint);
+        Blue::off(gpio);
+    }
+}

examples/blinky_clint.rs

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+#![no_std]
+
+extern crate hifive;
+
+use core::fmt::Write;
+use hifive::*;
+use hifive::prelude::*;
+use hifive::interrupt::Nr;
+
+fn main() {
+    let p = hifive::init(115_200);
+    led::init(p.GPIO0);
+
+    Red::on(p.GPIO0);
+
+    let plic = Plic(p.PLIC);
+    plic.init();
+
+    RtcConf::new().end(p.RTC);
+    Rtc(p.RTC).set_timeout(500.ms());
+
+    plic.set_priority(Interrupt::RTC, Priority::P7);
+    plic.enable(Interrupt::RTC);
+
+    let serial = Serial(p.UART0);
+    let mut stdout = Port(&serial);
+    writeln!(stdout, "External interrupts enabled: {}",
+             csr::mie.read().mext()).unwrap();
+    let threshold: u32 = plic.get_threshold().into();
+    writeln!(stdout, "PLIC threshold priority: {}",
+             threshold).unwrap();
+    writeln!(stdout, "RTC interrupt number: {}",
+             Interrupt::RTC.nr()).unwrap();
+    writeln!(stdout, "RTC interrupt enabled: {}",
+             plic.is_enabled(Interrupt::RTC)).unwrap();
+    let priority: u32 = plic.get_priority(Interrupt::RTC).into();
+    writeln!(stdout, "RTC interrupt priority: {}",
+             priority).unwrap();
+
+    unsafe {
+        interrupt::enable();
+    }
+}
+
+#[no_mangle]
+pub fn plic_trap_handler(p: &Peripherals, intr: &Interrupt) {
+    match *intr {
+        Interrupt::RTC => {
+            Rtc(p.RTC).restart();
+            Blue::toggle(p.GPIO0);
+        },
+        _ => {},
+    }
+}