Fix rebase syntax error; disable STIR test on armv6m

Author: Brandon Matthews

src/peripheral/dcb.rs

@@ -33,6 +33,7 @@ impl DCB {
     pub fn disable_trace(&mut self) {
         // unset bit 24 / TRCENA
         unsafe { self.demcr.modify(|w| w & !DCB_DEMCR_TRCENA); }
+    }
 
     /// Is there a debugger attached? (see notes)
     ///

src/peripheral/test.rs

@@ -109,6 +109,7 @@ fn nvic() {
     assert_eq!(address(&nvic.icpr), 0xE000E280);
     assert_eq!(address(&nvic.iabr), 0xE000E300);
     assert_eq!(address(&nvic.ipr), 0xE000E400);
+    #[cfg(not(armv6m))]
     assert_eq!(address(&nvic.stir), 0xE000EF00);
 }