Add riscv-peripheral changes as well

Author: romancardenas

riscv-pac/Cargo.toml

@@ -2,7 +2,7 @@
 name = "riscv-pac"
 version = "0.2.0"
 edition = "2021"
-rust-version = "1.61"
+rust-version = "1.60"
 repository = "https://github.com/rust-embedded/riscv"
 authors = ["The RISC-V Team <[email protected]>"]
 categories = ["embedded", "hardware-support", "no-std"]

riscv-peripheral/CHANGELOG.md

@@ -13,7 +13,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Changed
 
-- Bump `riscv-pac` version
+- `PLIC` now expects interrupt enums to implement the `riscv_pac::ExternalInterruptNumber` trait.
 
 ### Fixed
 

riscv-peripheral/Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "riscv-peripheral"
-version = "0.1.0"
+version = "0.2.0"
 edition = "2021"
 rust-version = "1.75"
 repository = "https://github.com/rust-embedded/riscv"

riscv-peripheral/examples/e310x.rs

@@ -2,17 +2,18 @@
 //! This is a simple example of how to use the `riscv-peripheral` crate to generate
 //! peripheral definitions for a target.
 
-use riscv_pac::result::{Error, Result};
-use riscv_pac::{HartIdNumber, InterruptNumber, PriorityNumber};
+use riscv_pac::{
+    result::{Error, Result},
+    ExternalInterruptNumber, HartIdNumber, InterruptNumber, PriorityNumber,
+};
 
-#[repr(u16)]
 #[derive(Clone, Copy, Debug, Eq, PartialEq)]
 pub enum HartId {
     H0 = 0,
 }
 
 unsafe impl HartIdNumber for HartId {
-    const MAX_HART_ID_NUMBER: u16 = 0;
+    const MAX_HART_ID_NUMBER: u16 = Self::H0 as u16;
 
     #[inline]
     fn number(self) -> u16 {
@@ -86,7 +87,7 @@ pub enum Interrupt {
 }
 
 unsafe impl InterruptNumber for Interrupt {
-    const MAX_INTERRUPT_NUMBER: usize = 52;
+    const MAX_INTERRUPT_NUMBER: usize = Self::I2C0 as usize;
 
     #[inline]
     fn number(self) -> usize {
@@ -104,8 +105,9 @@ unsafe impl InterruptNumber for Interrupt {
     }
 }
 
+unsafe impl ExternalInterruptNumber for Interrupt {}
+
 #[derive(Copy, Clone, Debug, PartialEq, Eq)]
-#[repr(u8)]
 pub enum Priority {
     P0 = 0,
     P1 = 1,
@@ -118,7 +120,7 @@ pub enum Priority {
 }
 
 unsafe impl PriorityNumber for Priority {
-    const MAX_PRIORITY_NUMBER: u8 = 7;
+    const MAX_PRIORITY_NUMBER: u8 = Self::P7 as u8;
 
     #[inline]
     fn number(self) -> u8 {

riscv-peripheral/src/lib.rs

@@ -9,6 +9,7 @@
 #![no_std]
 
 pub use riscv; // re-export riscv crate to allow macros to use it
+pub use riscv_pac::result; // re-export the result module
 
 pub mod common; // common definitions for all peripherals
 pub mod hal; // trait implementations for embedded-hal

riscv-peripheral/src/macros.rs

@@ -3,10 +3,12 @@
 /// Macro to create interfaces to CLINT peripherals in PACs.
 /// The resulting struct will be named `CLINT`, and will provide safe access to the CLINT registers.
 ///
-/// This macro expects 4 different argument types:
+/// This macro expects 5 different argument types:
 ///
 /// - Base address (**MANDATORY**): base address of the CLINT peripheral of the target.
 /// - Frequency (**OPTIONAL**): clock frequency (in Hz) of the `MTIME` register. It enables the `delay` method of the `CLINT` struct.
+/// - Async flag (**OPTIONAL**): It enables the `async_delay` method of the `CLINT struct`.
+///   You must activate the `embedded-hal-async` feature to use this flag.
 /// - Per-HART mtimecmp registers (**OPTIONAL**): a list of `mtimecmp` registers for easing access to per-HART mtimecmp regs.
 /// - Per-HART msip registers (**OPTIONAL**): a list of `msip` registers for easing access to per-HART msip regs.
 ///
@@ -17,41 +19,37 @@
 /// ## Base address only
 ///
 /// ```
-/// use riscv_peripheral::clint_codegen;
-///
-/// clint_codegen!(base 0x0200_0000, freq 32_768,); // do not forget the ending comma!
+/// riscv_peripheral::clint_codegen!(base 0x0200_0000, freq 32_768,); // do not forget the ending comma!
 ///
-/// let mswi = CLINT::mswi(); // MSWI peripheral
+/// let mswi = CLINT::mswi();     // MSWI peripheral
 /// let mtimer = CLINT::mtimer(); // MTIMER peripheral
-/// let delay = CLINT::delay(); // For the `embedded_hal::delay::DelayNs` trait
+/// let delay = CLINT::delay();   // For the `embedded_hal::delay::DelayNs` trait
 /// ```
 ///
 /// ## Base address and per-HART mtimecmp registers
 ///
 /// ```
-/// use riscv_peripheral::clint_codegen;
 /// use riscv_pac::result::{Error, Result};
 ///
 /// /// HART IDs for the target CLINT peripheral
 /// #[derive(Clone, Copy, Debug, Eq, PartialEq)]
-/// #[repr(u16)]
 /// pub enum HartId { H0 = 0, H1 = 1, H2 = 2 }
 ///
 /// // Implement `HartIdNumber` for `HartId`
 /// unsafe impl riscv_peripheral::aclint::HartIdNumber for HartId {
 ///   const MAX_HART_ID_NUMBER: u16 = 2;
 ///   fn number(self) -> u16 { self as _ }
 ///   fn from_number(number: u16) -> Result<Self> {
-///     if number > Self::MAX_HART_ID_NUMBER {
-///        Err(Error::InvalidVariant(number as usize))
-///     } else {
-///        // SAFETY: valid context number
-///        Ok(unsafe { core::mem::transmute(number) })
+///     match number {
+///      0 => Ok(HartId::H0),
+///      1 => Ok(HartId::H1),
+///      2 => Ok(HartId::H2),
+///      _ => Err(Error::InvalidVariant(number as _)),
 ///     }
 ///   }
 /// }
 ///
-/// clint_codegen!(
+/// riscv_peripheral::clint_codegen!(
 ///     base 0x0200_0000,
 ///     mtimecmps [mtimecmp0 = (HartId::H0, "`H0`"), mtimecmp1 = (HartId::H1, "`H1`"), mtimecmp2 = (HartId::H2, "`H2`")],
 ///     msips [msip0=(HartId::H0,"`H0`"), msip1=(HartId::H1,"`H1`"), msip2=(HartId::H2,"`H2`")], // do not forget the ending comma!
@@ -206,7 +204,7 @@ macro_rules! clint_codegen {
             ///
             /// # Note
             ///
-            /// You must export the `riscv_peripheral::hal::delay::DelayNs` trait in order to use delay methods.
+            /// You must export the [`embedded_hal::delay::DelayNs`] trait in order to use delay methods.
             #[inline]
             pub const fn delay() -> $crate::hal::aclint::Delay {
                 $crate::hal::aclint::Delay::new(Self::mtime(), Self::freq())
@@ -220,7 +218,7 @@ macro_rules! clint_codegen {
             ///
             /// # Note
             ///
-            /// You must export the `riscv_peripheral::hal_async::delay::DelayNs` trait in order to use delay methods.
+            /// You must export the [`embedded_hal_async::delay::DelayNs`] trait in order to use delay methods.
             ///
             /// This implementation relies on the machine-level timer interrupts to wake futures.
             /// Therefore, it needs to schedule the machine-level timer interrupts via the `MTIMECMP` register assigned to the current HART.
@@ -264,6 +262,27 @@ macro_rules! clint_codegen {
 }
 
 /// Macro to create interfaces to PLIC peripherals in PACs.
+/// The resulting struct will be named `PLIC`, and will provide safe access to the PLIC registers.
+///
+/// This macro expects 2 different argument types:
+///
+/// - Base address (**MANDATORY**): base address of the PLIC peripheral of the target.
+/// - Per-HART contexts (**OPTIONAL**): a list of `ctx` contexts for easing access to per-HART PLIC contexts.
+///
+/// Check the examples below for more details about the usage and syntax of this macro.
+///
+/// # Example
+///
+/// ## Base address only
+///
+/// ```
+/// use riscv_peripheral::clint_codegen;
+///
+/// riscv_peripheral::plic_codegen!(base 0x0C00_0000,); // do not forget the ending comma!
+///
+/// let priorities = PLIC::priorities(); // Priorities registers
+/// let pendings = PLIC::pendings();     // Pendings registers
+/// ```
 #[macro_export]
 macro_rules! plic_codegen {
     () => {

riscv-peripheral/src/plic.rs

@@ -145,11 +145,11 @@ impl<P: Plic> CTX<P> {
 
 #[cfg(test)]
 pub(crate) mod test {
-    use super::{HartIdNumber, InterruptNumber, PriorityNumber};
     use riscv_pac::result::{Error, Result};
+    use riscv_pac::{ExternalInterruptNumber, HartIdNumber, InterruptNumber, PriorityNumber};
 
     #[derive(Clone, Copy, Debug, Eq, PartialEq)]
-    #[repr(u16)]
+    #[repr(usize)]
     pub(crate) enum Interrupt {
         I1 = 1,
         I2 = 2,
@@ -194,6 +194,8 @@ pub(crate) mod test {
         }
     }
 
+    unsafe impl ExternalInterruptNumber for Interrupt {}
+
     unsafe impl PriorityNumber for Priority {
         const MAX_PRIORITY_NUMBER: u8 = 3;
 

riscv-peripheral/src/plic/claim.rs

@@ -1,14 +1,15 @@
 //! Interrupt claim/complete register
 
-use crate::{common::unsafe_peripheral, plic::InterruptNumber};
+use crate::common::unsafe_peripheral;
+use riscv_pac::ExternalInterruptNumber;
 
 unsafe_peripheral!(CLAIM, u32, RW);
 
 impl CLAIM {
     /// Claims the number of a pending interrupt for for the PLIC context.
     /// If no interrupt is pending for this context, it returns [`None`].
     #[inline]
-    pub fn claim<I: InterruptNumber>(self) -> Option<I> {
+    pub fn claim<I: ExternalInterruptNumber>(self) -> Option<I> {
         match self.register.read() {
             0 => None,
             i => Some(I::from_number(i as _).unwrap()),
@@ -22,7 +23,7 @@ impl CLAIM {
     /// If the source ID does not match an interrupt source that is
     /// currently enabled for the target, the completion is silently ignored.
     #[inline]
-    pub fn complete<I: InterruptNumber>(self, source: I) {
+    pub fn complete<I: ExternalInterruptNumber>(self, source: I) {
         self.register.write(source.number() as _)
     }
 }
@@ -31,6 +32,7 @@ impl CLAIM {
 mod test {
     use super::super::test::Interrupt;
     use super::*;
+    use riscv_pac::InterruptNumber;
 
     #[test]
     fn test_claim() {

riscv-peripheral/src/plic/enables.rs

@@ -1,9 +1,7 @@
 //! Interrupt enables register of a PLIC context.
 
-use crate::{
-    common::{Reg, RW},
-    plic::InterruptNumber,
-};
+use crate::common::{Reg, RW};
+use riscv_pac::ExternalInterruptNumber;
 
 /// Enables register of a PLIC context.
 #[derive(Clone, Copy, Debug, Eq, PartialEq)]
@@ -31,8 +29,8 @@ impl ENABLES {
 
     /// Checks if an interrupt source is enabled for the PLIC context.
     #[inline]
-    pub fn is_enabled<I: InterruptNumber>(self, source: I) -> bool {
-        let source = source.number() as usize;
+    pub fn is_enabled<I: ExternalInterruptNumber>(self, source: I) -> bool {
+        let source = source.number();
         let offset = (source / u32::BITS as usize) as _;
         // SAFETY: valid interrupt number
         let reg: Reg<u32, RW> = unsafe { Reg::new(self.ptr.offset(offset)) };
@@ -49,8 +47,8 @@ impl ENABLES {
     ///
     /// * Enabling an interrupt source can break mask-based critical sections.
     #[inline]
-    pub unsafe fn enable<I: InterruptNumber>(self, source: I) {
-        let source = source.number() as usize;
+    pub unsafe fn enable<I: ExternalInterruptNumber>(self, source: I) {
+        let source = source.number();
         let offset = (source / u32::BITS as usize) as _;
         // SAFETY: valid interrupt number
         let reg: Reg<u32, RW> = unsafe { Reg::new(self.ptr.offset(offset)) };
@@ -70,12 +68,12 @@ impl ENABLES {
     /// * Register must be properly aligned **for atomic operations**.
     /// * The register must not be accessed through non-atomic operations until this function returns.
     #[inline]
-    pub unsafe fn atomic_enable<I: InterruptNumber>(
+    pub unsafe fn atomic_enable<I: ExternalInterruptNumber>(
         self,
         source: I,
         order: core::sync::atomic::Ordering,
     ) {
-        let source = source.number() as usize;
+        let source = source.number();
         let offset = (source / u32::BITS as usize) as _;
         // SAFETY: valid interrupt number
         let reg: Reg<u32, RW> = unsafe { Reg::new(self.ptr.offset(offset)) };
@@ -88,8 +86,8 @@ impl ENABLES {
     ///
     /// It performs non-atomic read-modify-write operations, which may lead to **wrong** behavior.
     #[inline]
-    pub fn disable<I: InterruptNumber>(self, source: I) {
-        let source = source.number() as usize;
+    pub fn disable<I: ExternalInterruptNumber>(self, source: I) {
+        let source = source.number();
         let offset = (source / u32::BITS as usize) as _;
         // SAFETY: valid interrupt number
         let reg: Reg<u32, RW> = unsafe { Reg::new(self.ptr.offset(offset)) };
@@ -108,12 +106,12 @@ impl ENABLES {
     /// * Register must be properly aligned **for atomic operations**.
     /// * The register must not be accessed through non-atomic operations until this function returns.
     #[inline]
-    pub unsafe fn atomic_disable<I: InterruptNumber>(
+    pub unsafe fn atomic_disable<I: ExternalInterruptNumber>(
         self,
         source: I,
         order: core::sync::atomic::Ordering,
     ) {
-        let source = source.number() as usize;
+        let source = source.number();
         let offset = (source / u32::BITS as usize) as _;
         // SAFETY: valid interrupt number
         let reg: Reg<u32, RW> = unsafe { Reg::new(self.ptr.offset(offset)) };
@@ -126,7 +124,7 @@ impl ENABLES {
     ///
     ///* Enabling all interrupt sources can break mask-based critical sections.
     #[inline]
-    pub unsafe fn enable_all<I: InterruptNumber>(self) {
+    pub unsafe fn enable_all<I: ExternalInterruptNumber>(self) {
         for offset in 0..=(I::MAX_INTERRUPT_NUMBER as u32 / u32::BITS) as isize {
             // SAFETY: valid offset
             let reg: Reg<u32, RW> = unsafe { Reg::new(self.ptr.offset(offset)) };
@@ -136,7 +134,7 @@ impl ENABLES {
 
     /// Disables all the external interrupt sources for the PLIC context.
     #[inline]
-    pub fn disable_all<I: InterruptNumber>(self) {
+    pub fn disable_all<I: ExternalInterruptNumber>(self) {
         for offset in 0..=(I::MAX_INTERRUPT_NUMBER as u32 / u32::BITS) as _ {
             // SAFETY: valid offset
             let reg: Reg<u32, RW> = unsafe { Reg::new(self.ptr.offset(offset)) };

riscv-peripheral/src/plic/pendings.rs

@@ -1,9 +1,7 @@
 //! Interrupt pending bits register.
 
-use crate::{
-    common::{Reg, RO},
-    plic::InterruptNumber,
-};
+use crate::common::{Reg, RO};
+use riscv_pac::ExternalInterruptNumber;
 
 /// Interrupts pending bits register.
 #[derive(Clone, Copy, Debug, Eq, PartialEq)]
@@ -31,8 +29,8 @@ impl PENDINGS {
 
     /// Checks if an interrupt triggered by a given source is pending.
     #[inline]
-    pub fn is_pending<I: InterruptNumber>(self, source: I) -> bool {
-        let source = source.number() as usize;
+    pub fn is_pending<I: ExternalInterruptNumber>(self, source: I) -> bool {
+        let source = source.number();
         let offset = (source / u32::BITS as usize) as _;
         // SAFETY: valid interrupt number
         let reg: Reg<u32, RO> = unsafe { Reg::new(self.ptr.offset(offset)) };