@@ -194,44 +194,48 @@ pub fn compute_abi_info<'a, 'tcx>(cx: &CodegenCx<'a, 'tcx>, fty: &mut FnType<'tc
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let mut sse_regs = 8 ; // XMM0-7
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let mut x86_64_ty = |arg : & mut ArgType < ' tcx > , is_arg : bool | {
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- let cls = classify_arg ( cx, arg) ;
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+ let mut cls_or_mem = classify_arg ( cx, arg) ;
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let mut needed_int = 0 ;
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let mut needed_sse = 0 ;
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- let in_mem = match cls {
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- Err ( Memory ) => true ,
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- Ok ( ref cls) if is_arg => {
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- for & c in cls {
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+ if is_arg {
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+ if let Ok ( cls) = cls_or_mem {
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+ for & c in & cls {
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match c {
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Class :: Int => needed_int += 1 ,
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Class :: Sse => needed_sse += 1 ,
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_ => { }
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}
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}
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- arg. layout . is_aggregate ( ) &&
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- ( int_regs < needed_int || sse_regs < needed_sse)
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+ if arg. layout . is_aggregate ( ) {
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+ if int_regs < needed_int || sse_regs < needed_sse {
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+ cls_or_mem = Err ( Memory ) ;
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+ }
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+ }
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}
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- Ok ( _) => false
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- } ;
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+ }
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- if in_mem {
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- if is_arg {
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- arg. make_indirect_byval ( ) ;
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- } else {
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- // `sret` parameter thus one less integer register available
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- arg. make_indirect ( ) ;
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- int_regs -= 1 ;
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+ match cls_or_mem {
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+ Err ( Memory ) => {
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+ if is_arg {
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+ arg. make_indirect_byval ( ) ;
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+ } else {
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+ // `sret` parameter thus one less integer register available
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+ arg. make_indirect ( ) ;
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+ int_regs -= 1 ;
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+ }
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}
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- } else {
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- // split into sized chunks passed individually
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- int_regs -= needed_int;
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- sse_regs -= needed_sse;
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-
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- if arg. layout . is_aggregate ( ) {
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- let size = arg. layout . size ;
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- arg. cast_to ( cast_target ( cls. as_ref ( ) . unwrap ( ) , size) )
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- } else {
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- arg. extend_integer_width_to ( 32 ) ;
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+ Ok ( ref cls) => {
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+ // split into sized chunks passed individually
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+ int_regs -= needed_int;
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+ sse_regs -= needed_sse;
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+
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+ if arg. layout . is_aggregate ( ) {
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+ let size = arg. layout . size ;
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+ arg. cast_to ( cast_target ( cls, size) )
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+ } else {
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+ arg. extend_integer_width_to ( 32 ) ;
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+ }
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}
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}
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} ;
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