@@ -48,11 +48,10 @@ impl<'bcx, 'tcx> MirContext<'bcx, 'tcx> {
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}
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mir:: Terminator :: Switch { ref discr, ref adt_def, ref targets } => {
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- let adt_ty = bcx. tcx ( ) . lookup_item_type ( adt_def. did ) . ty ;
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- let represented_ty = adt:: represent_type ( bcx. ccx ( ) , adt_ty) ;
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-
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let discr_lvalue = self . trans_lvalue ( bcx, discr) ;
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- let discr = adt:: trans_get_discr ( bcx, & represented_ty, discr_lvalue. llval , None ) ;
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+ let ty = discr_lvalue. ty . to_ty ( bcx. tcx ( ) ) ;
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+ let repr = adt:: represent_type ( bcx. ccx ( ) , ty) ;
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+ let discr = adt:: trans_get_discr ( bcx, & repr, discr_lvalue. llval , None ) ;
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// The else branch of the Switch can't be hit, so branch to an unreachable
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// instruction so LLVM knows that
@@ -61,7 +60,7 @@ impl<'bcx, 'tcx> MirContext<'bcx, 'tcx> {
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let switch = build:: Switch ( bcx, discr, unreachable_blk. llbb , targets. len ( ) ) ;
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assert_eq ! ( adt_def. variants. len( ) , targets. len( ) ) ;
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for ( adt_variant, target) in adt_def. variants . iter ( ) . zip ( targets) {
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- let llval = adt:: trans_case ( bcx, & * represented_ty , adt_variant. disr_val ) ;
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+ let llval = adt:: trans_case ( bcx, & * repr , adt_variant. disr_val ) ;
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let llbb = self . llblock ( * target) ;
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build:: AddCase ( switch, llval, llbb)
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