@@ -322,20 +322,21 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
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}
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assert_eq!( a. layout( ) , b. layout( ) ) ;
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assert_eq!( a. layout( ) , c. layout( ) ) ;
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- let layout = a . layout( ) ;
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+ assert_eq! ( a . layout( ) , ret . layout( ) ) ;
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- let ( lane_count, _lane_ty) = layout. ty. simd_size_and_type( fx. tcx) ;
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- let ( ret_lane_count, ret_lane_ty) = ret. layout( ) . ty. simd_size_and_type( fx. tcx) ;
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- assert_eq!( lane_count, ret_lane_count) ;
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- let ret_lane_layout = fx. layout_of( ret_lane_ty) ;
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+ let layout = a. layout( ) ;
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+ let ( lane_count, lane_ty) = layout. ty. simd_size_and_type( fx. tcx) ;
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for lane in 0 ..lane_count {
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- let a_lane = a. value_lane( fx, lane) . load_scalar ( fx ) ;
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- let b_lane = b. value_lane( fx, lane) . load_scalar ( fx ) ;
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- let c_lane = c. value_lane( fx, lane) . load_scalar ( fx ) ;
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+ let a_lane = a. value_lane( fx, lane) ;
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+ let b_lane = b. value_lane( fx, lane) ;
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+ let c_lane = c. value_lane( fx, lane) ;
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- let mul_lane = fx. bcx. ins( ) . fmul( a_lane, b_lane) ;
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- let res_lane = CValue :: by_val( fx. bcx. ins( ) . fadd( mul_lane, c_lane) , ret_lane_layout) ;
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+ let res_lane = match lane_ty. kind( ) {
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+ ty:: Float ( FloatTy :: F32 ) => fx. easy_call( "fmaf" , & [ a_lane, b_lane, c_lane] , lane_ty) ,
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+ ty:: Float ( FloatTy :: F64 ) => fx. easy_call( "fma" , & [ a_lane, b_lane, c_lane] , lane_ty) ,
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+ _ => unreachable!( ) ,
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+ } ;
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ret. place_lane( fx, lane) . write_cvalue( fx, res_lane) ;
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}
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