|
1354 | 1354 | * [x] [`_mm512_permute_ps`]
|
1355 | 1355 | * [x] [`_mm512_mask_permute_ps`]
|
1356 | 1356 | * [x] [`_mm512_maskz_permute_ps`]
|
1357 |
| - |
| 1357 | + * [x] [`_mm_mask_permute_ps`] |
| 1358 | + * [x] [`_mm_maskz_permute_ps`] |
| 1359 | + * [x] [`_mm256_mask_permute_ps`] |
| 1360 | + * [x] [`_mm256_maskz_permute_ps`] |
1358 | 1361 | * [x] [`_mm512_permute_pd`]
|
1359 | 1362 | * [x] [`_mm512_mask_permute_pd`]
|
1360 | 1363 | * [x] [`_mm512_maskz_permute_pd`]
|
1361 |
| - |
| 1364 | + * [x] [`_mm_mask_permute_pd`] |
| 1365 | + * [x] [`_mm_maskz_permute_pd`] |
| 1366 | + * [x] [`_mm256_mask_permute_pd`] |
| 1367 | + * [x] [`_mm256_maskz_permute_pd`] |
1362 | 1368 | * [x] [`_mm512_permutevar_epi32`]
|
1363 | 1369 | * [x] [`_mm512_mask_permutevar_epi32`]
|
1364 |
| - |
1365 | 1370 | * [x] [`_mm512_permutevar_ps`]
|
1366 | 1371 | * [x] [`_mm512_mask_permutevar_ps`]
|
1367 | 1372 | * [x] [`_mm512_maskz_permutevar_ps`]
|
1368 |
| - |
| 1373 | + * [x] [`_mm_mask_permutevar_ps`] |
| 1374 | + * [x] [`_mm_maskz_permutevar_ps`] |
| 1375 | + * [x] [`_mm256_mask_permutevar_ps`] |
| 1376 | + * [x] [`_mm256_maskz_permutevar_ps`] |
1369 | 1377 | * [x] [`_mm512_permutevar_pd`]
|
1370 | 1378 | * [x] [`_mm512_mask_permutevar_pd`]
|
1371 | 1379 | * [x] [`_mm512_maskz_permutevar_pd`]
|
1372 |
| - |
| 1380 | + * [x] [`_mm_mask_permutevar_pd`] |
| 1381 | + * [x] [`_mm_maskz_permutevar_pd`] |
| 1382 | + * [x] [`_mm256_mask_permutevar_pd`] |
| 1383 | + * [x] [`_mm256_maskz_permutevar_pd`] |
1373 | 1384 | * [x] [`_mm512_permutex2var_epi32`]
|
1374 | 1385 | * [x] [`_mm512_mask_permutex2var_epi32`]
|
1375 | 1386 | * [x] [`_mm512_maskz_permutex2var_epi32`]
|
1376 | 1387 | * [x] [`_mm512_mask2_permutex2var_epi32`]
|
1377 |
| - |
| 1388 | + * [x] [`_mm_mask_permutex2var_epi32`] |
| 1389 | + * [x] [`_mm_mask2_permutex2var_epi32`] |
| 1390 | + * [x] [`_mm_maskz_permutex2var_epi32`] |
| 1391 | + * [x] [`_mm_permutex2var_epi32`] |
| 1392 | + * [x] [`_mm256_mask_permutex2var_epi32`] |
| 1393 | + * [x] [`_mm256_mask2_permutex2var_epi32`] |
| 1394 | + * [x] [`_mm256_maskz_permutex2var_epi32`] |
| 1395 | + * [x] [`_mm256_permutex2var_epi32`] |
1378 | 1396 | * [x] [`_mm512_permutex2var_epi64`]
|
1379 | 1397 | * [x] [`_mm512_mask_permutex2var_epi64`]
|
1380 | 1398 | * [x] [`_mm512_maskz_permutex2var_epi64`]
|
1381 | 1399 | * [x] [`_mm512_mask2_permutex2var_epi64`]
|
1382 |
| - |
| 1400 | + * [x] [`_mm_mask_permutex2var_epi64`] |
| 1401 | + * [x] [`_mm_mask2_permutex2var_epi64`] |
| 1402 | + * [x] [`_mm_maskz_permutex2var_epi64`] |
| 1403 | + * [x] [`_mm_permutex2var_epi64`] |
| 1404 | + * [x] [`_mm256_mask_permutex2var_epi64`] |
| 1405 | + * [x] [`_mm256_mask2_permutex2var_epi64`] |
| 1406 | + * [x] [`_mm256_maskz_permutex2var_epi64`] |
| 1407 | + * [x] [`_mm256_permutex2var_epi64`] |
1383 | 1408 | * [x] [`_mm512_permutex2var_ps`]
|
1384 | 1409 | * [x] [`_mm512_mask_permutex2var_ps`]
|
1385 | 1410 | * [x] [`_mm512_maskz_permutex2var_ps`]
|
1386 | 1411 | * [x] [`_mm512_mask2_permutex2var_ps`]
|
1387 |
| - |
| 1412 | + * [x] [`_mm_mask_permutex2var_ps`] |
| 1413 | + * [x] [`_mm_mask2_permutex2var_ps`] |
| 1414 | + * [x] [`_mm_maskz_permutex2var_ps`] |
| 1415 | + * [x] [`_mm_permutex2var_ps`] |
| 1416 | + * [x] [`_mm256_mask_permutex2var_ps`] |
| 1417 | + * [x] [`_mm256_mask2_permutex2var_ps`] |
| 1418 | + * [x] [`_mm256_maskz_permutex2var_ps`] |
| 1419 | + * [x] [`_mm256_permutex2var_ps`] |
1388 | 1420 | * [x] [`_mm512_permutex2var_pd`]
|
1389 | 1421 | * [x] [`_mm512_mask_permutex2var_pd`]
|
1390 | 1422 | * [x] [`_mm512_maskz_permutex2var_pd`]
|
1391 | 1423 | * [x] [`_mm512_mask2_permutex2var_pd`]
|
1392 |
| - |
| 1424 | + * [x] [`_mm_mask_permutex2var_pd`] |
| 1425 | + * [x] [`_mm_mask2_permutex2var_pd`] |
| 1426 | + * [x] [`_mm_maskz_permutex2var_pd`] |
| 1427 | + * [x] [`_mm_permutex2var_pd`] |
| 1428 | + * [x] [`_mm256_mask_permutex2var_pd`] |
| 1429 | + * [x] [`_mm256_mask2_permutex2var_pd`] |
| 1430 | + * [x] [`_mm256_maskz_permutex2var_pd`] |
| 1431 | + * [x] [`_mm256_permutex2var_pd`] |
1393 | 1432 | * [x] [`_mm512_permutex_epi64`]
|
1394 | 1433 | * [x] [`_mm512_mask_permutex_epi64`]
|
1395 | 1434 | * [x] [`_mm512_maskz_permutex_epi64`]
|
1396 |
| - |
| 1435 | + * [x] [`_mm256_mask_permutex_epi64`] |
| 1436 | + * [x] [`_mm256_maskz_permutex_epi64`] |
| 1437 | + * [x] [`_mm256_permutex_epi64`] |
1397 | 1438 | * [x] [`_mm512_permutex_pd`]
|
1398 | 1439 | * [x] [`_mm512_mask_permutex_pd`]
|
1399 | 1440 | * [x] [`_mm512_maskz_permutex_pd`]
|
1400 |
| - |
| 1441 | + * [x] [`_mm256_mask_permutex_pd`] |
| 1442 | + * [x] [`_mm256_maskz_permutex_pd`] |
| 1443 | + * [x] [`_mm256_permutex_pd`] |
1401 | 1444 | * [x] [`_mm512_permutexvar_epi32`]
|
1402 | 1445 | * [x] [`_mm512_mask_permutexvar_epi32`]
|
1403 | 1446 | * [x] [`_mm512_maskz_permutexvar_epi32`]
|
1404 |
| - |
| 1447 | + * [x] [`_mm256_mask_permutexvar_epi32`] |
| 1448 | + * [x] [`_mm256_maskz_permutexvar_epi32`] |
| 1449 | + * [x] [`_mm256_permutexvar_epi32`] |
1405 | 1450 | * [x] [`_mm512_permutexvar_epi64`]
|
1406 | 1451 | * [x] [`_mm512_mask_permutexvar_epi64`]
|
1407 | 1452 | * [x] [`_mm512_maskz_permutexvar_epi64`]
|
1408 |
| - |
| 1453 | + * [x] [`_mm256_mask_permutexvar_epi64`] |
| 1454 | + * [x] [`_mm256_maskz_permutexvar_epi64`] |
| 1455 | + * [x] [`_mm256_permutexvar_epi64`] |
1409 | 1456 | * [x] [`_mm512_permutexvar_ps`]
|
1410 | 1457 | * [x] [`_mm512_mask_permutexvar_ps`]
|
1411 | 1458 | * [x] [`_mm512_maskz_permutexvar_ps`]
|
1412 |
| - |
| 1459 | + * [x] [`_mm256_mask_permutexvar_ps`] |
| 1460 | + * [x] [`_mm256_maskz_permutexvar_ps`] |
| 1461 | + * [x] [`_mm256_permutexvar_ps`] |
1413 | 1462 | * [x] [`_mm512_permutexvar_pd`]
|
1414 | 1463 | * [x] [`_mm512_mask_permutexvar_pd`]
|
1415 | 1464 | * [x] [`_mm512_maskz_permutexvar_pd`]
|
| 1465 | + * [x] [`_mm256_mask_permutexvar_pd`] |
| 1466 | + * [x] [`_mm256_maskz_permutexvar_pd`] |
| 1467 | + * [x] [`_mm256_permutexvar_pd`] |
| 1468 | + * [x] [`_mm512_i32gather_epi32`] |
| 1469 | + * [x] [`_mm512_mask_i32gather_epi32`] |
| 1470 | + * [_] [`_mm_mmask_i32gather_epi32`] //need i1 |
| 1471 | + * [_] [`_mm256_mmask_i32gather_epi32`] //need i1 |
| 1472 | + * [x] [`_mm512_i32gather_epi64`] |
| 1473 | + * [x] [`_mm512_mask_i32gather_epi64`] |
| 1474 | + * [_] [`_mm_mmask_i32gather_epi64`] //need i1 |
| 1475 | + * [_] [`_mm256_mmask_i32gather_epi64`] //need i1 |
| 1476 | + * [x] [`_mm512_i32gather_ps`] |
| 1477 | + * [x] [`_mm512_mask_i32gather_ps`] |
| 1478 | + * [_] [`_mm_mmask_i32gather_ps`] //need i1 |
| 1479 | + * [_] [`_mm256_mmask_i32gather_ps`] //need i1 |
| 1480 | + * [x] [`_mm512_i32gather_pd`] |
| 1481 | + * [x] [`_mm512_mask_i32gather_pd`] |
| 1482 | + * [_] [`_mm_mmask_i32gather_pd`] //need i1 |
| 1483 | + * [_] [`_mm256_mmask_i32gather_pd`] //need i1 |
| 1484 | + * [x] [`_mm512_i64gather_epi32`] |
| 1485 | + * [x] [`_mm512_mask_i64gather_epi32`] |
| 1486 | + * [_] [`_mm_mmask_i64gather_epi32`] //need i1 |
| 1487 | + * [_] [`_mm256_mmask_i64gather_epi32`] //need i1 |
| 1488 | + * [x] [`_mm512_i64gather_epi64`] |
| 1489 | + * [x] [`_mm512_mask_i64gather_epi64`] |
| 1490 | + * [_] [`_mm_mmask_i64gather_epi64`] //need i1 |
| 1491 | + * [_] [`_mm256_mmask_i64gather_epi64`] //need i1 |
| 1492 | + * [x] [`_mm512_i64gather_ps`] |
| 1493 | + * [x] [`_mm512_mask_i64gather_ps`] |
| 1494 | + * [_] [`_mm_mmask_i64gather_ps`] //need i1 |
| 1495 | + * [_] [`_mm256_mmask_i64gather_ps`] //need i1 |
| 1496 | + * [x] [`_mm512_i64gather_pd`] |
| 1497 | + * [x] [`_mm512_mask_i64gather_pd`] |
| 1498 | + * [_] [`_mm_mmask_i64gather_pd`] //need i1 |
| 1499 | + * [_] [`_mm256_mmask_i64gather_pd`] //need i1 |
| 1500 | + * [ ] [`_mm512_i32extgather_epi32`] //not in llvm |
| 1501 | + * [ ] [`_mm512_mask_i32extgather_epi32`] //not in llvm |
| 1502 | + * [ ] [`_mm512_i32extgather_ps`] // not in llvm |
| 1503 | + * [ ] [`_mm512_mask_i32extgather_ps`] //not in llvm |
| 1504 | + * [ ] [`_mm512_i32loextgather_epi64`] //not in llvm |
| 1505 | + * [ ] [`_mm512_mask_i32loextgather_epi64`] //not in llvm |
| 1506 | + * [ ] [`_mm512_i32loextgather_pd`] //not in llvm |
| 1507 | + * [ ] [`_mm512_mask_i32loextgather_pd`] //not in llvm |
| 1508 | + * [ ] [`_mm512_i32logather_epi64`] //not in llvm |
| 1509 | + * [ ] [`_mm512_mask_i32logather_epi64`] //not in llvm |
| 1510 | + * [ ] [`_mm512_i32logather_pd`] //not in llvm |
| 1511 | + * [ ] [`_mm512_mask_i32logather_pd`] //not in llvm |
| 1512 | + * [x] [`_mm512_i32scatter_epi32`] |
| 1513 | + * [x] [`_mm512_mask_i32scatter_epi32`] |
| 1514 | + * [_] [`_mm_i32scatter_epi32`] //need i1 |
| 1515 | + * [_] [`_mm_mask_i32scatter_epi32`] // need i1 |
| 1516 | + * [_] [`_mm256_i32scatter_epi32`] //need i1 |
| 1517 | + * [_] [`_mm256_mask_i32scatter_epi32`] //need i1 |
| 1518 | + * [x] [`_mm512_i32scatter_epi64`] |
| 1519 | + * [x] [`_mm512_mask_i32scatter_epi64`] |
| 1520 | + * [_] [`_mm_i32scatter_epi64`]//need i1 |
| 1521 | + * [_] [`_mm_mask_i32scatter_epi64`] //need i1 |
| 1522 | + * [_] [`_mm256_i32scatter_epi64`] //need i1 |
| 1523 | + * [_] [`_mm256_mask_i32scatter_epi64`] //need i1 |
| 1524 | + * [x] [`_mm512_i32scatter_ps`] |
| 1525 | + * [x] [`_mm512_mask_i32scatter_ps`] |
| 1526 | + * [_] [`_mm_i32scatter_ps`] //need i1 |
| 1527 | + * [_] [`_mm_mask_i32scatter_ps`] //need i1 |
| 1528 | + * [_] [`_mm256_i32scatter_ps`] //need i1 |
| 1529 | + * [_] [`_mm256_mask_i32scatter_ps`] //need i1 |
| 1530 | + * [x] [`_mm512_i32scatter_pd`] |
| 1531 | + * [x] [`_mm512_mask_i32scatter_pd`] |
| 1532 | + * [_] [`_mm_i32scatter_pd`] //need i1 |
| 1533 | + * [_] [`_mm_mask_i32scatter_pd`] //need i1 |
| 1534 | + * [_] [`_mm256_i32scatter_pd`] //need i1 |
| 1535 | + * [_] [`_mm256_mask_i32scatter_pd`] //need i1 |
| 1536 | + * [x] [`_mm512_i64scatter_epi32`] |
| 1537 | + * [x] [`_mm512_mask_i64scatter_epi32`] |
| 1538 | + * [_] [`_mm_i64scatter_epi32`] //need i1 |
| 1539 | + * [_] [`_mm_mask_i64scatter_epi32`] //need i1 |
| 1540 | + * [_] [`_mm256_i64scatter_epi32`] //need i1 |
| 1541 | + * [_] [`_mm256_mask_i64scatter_epi32`] //need i1 |
| 1542 | + * [x] [`_mm512_mask_i64scatter_epi64`] |
| 1543 | + * [x] [`_mm512_i64scatter_epi64`] |
| 1544 | + * [_] [`_mm_i64scatter_epi64`] //need i1 |
| 1545 | + * [_] [`_mm_mask_i64scatter_epi64`] //need i1 |
| 1546 | + * [_] [`_mm256_i64scatter_epi64`] //need i1 |
| 1547 | + * [_] [`_mm256_mask_i64scatter_epi64`] //need i1 |
| 1548 | + * [x] [`_mm512_i64scatter_ps`] |
| 1549 | + * [x] [`_mm512_mask_i64scatter_ps`] |
| 1550 | + * [_] [`_mm_i64scatter_ps`] //need i1 |
| 1551 | + * [_] [`_mm_mask_i64scatter_ps`] //need i1 |
| 1552 | + * [_] [`_mm256_i64scatter_ps`] //need i1 |
| 1553 | + * [_] [`_mm256_mask_i64scatter_ps`] //need i1 |
| 1554 | + * [x] [`_mm512_i64scatter_pd`] |
| 1555 | + * [x] [`_mm512_mask_i64scatter_pd`] |
| 1556 | + * [_] [`_mm_i64scatter_pd`] //need i1 |
| 1557 | + * [_] [`_mm_mask_i64scatter_pd`] //need i1 |
| 1558 | + * [_] [`_mm256_i64scatter_pd`] //need i1 |
| 1559 | + * [_] [`_mm256_mask_i64scatter_pd`] //need i1 |
| 1560 | + * [ ] [`_mm512_i32extscatter_epi32`] //not in llvm |
| 1561 | + * [ ] [`_mm512_mask_i32extscatter_epi32`] //not in llvm |
| 1562 | + * [ ] [`_mm512_i32extscatter_ps`] //not in llvm |
| 1563 | + * [ ] [`_mm512_mask_i32extscatter_ps`] //not in llvm |
| 1564 | + * [ ] [`_mm512_i32loextscatter_epi64`] //not in llvm |
| 1565 | + * [ ] [`_mm512_mask_i32loextscatter_epi64`] //not in llvm |
| 1566 | + * [ ] [`_mm512_i32loextscatter_pd`] //not in llvm |
| 1567 | + * [ ] [`_mm512_mask_i32loextscatter_pd`] //not in llvm |
| 1568 | + * [ ] [`_mm512_i32loscatter_epi64`] //not in llvm |
| 1569 | + * [ ] [`_mm512_mask_i32loscatter_epi64`] //not in llvm |
| 1570 | + * [ ] [`_mm512_i32loscatter_pd`] //not in llvm |
| 1571 | + * [ ] [`_mm512_mask_i32loscatter_pd`] //not in llvm |
1416 | 1572 |
|
1417 | 1573 | * [x] [`_mm512_castpd128_pd512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castpd128_pd512&expand=5236)
|
1418 | 1574 | * [x] [`_mm512_castpd256_pd512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castpd256_pd512&expand=5236)
|
|
1495 | 1651 | * [x] [`_mm512_extractf64x4_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_extractf64x4_pd&expand=5236)
|
1496 | 1652 | * [x] [`_mm512_extracti32x4_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_extracti32x4_epi32&expand=5236)
|
1497 | 1653 | * [x] [`_mm512_extracti64x4_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_extracti64x4_epi64&expand=5236)
|
1498 |
| - * [ ] [`_mm512_i32extgather_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32extgather_epi32&expand=5236) |
1499 |
| - * [ ] [`_mm512_i32extgather_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32extgather_ps&expand=5236) |
1500 |
| - * [ ] [`_mm512_i32extscatter_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32extscatter_epi32&expand=5236) |
1501 |
| - * [ ] [`_mm512_i32extscatter_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32extscatter_ps&expand=5236) |
1502 |
| - * [x] [`_mm512_i32gather_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32gather_epi32&expand=5236) |
1503 |
| - * [x] [`_mm512_i32gather_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32gather_epi64&expand=5236) |
1504 |
| - * [x] [`_mm512_i32gather_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32gather_pd&expand=5236) |
1505 |
| - * [x] [`_mm512_i32gather_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32gather_ps&expand=5236) |
1506 |
| - * [ ] [`_mm512_i32loextgather_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32loextgather_epi64&expand=5236) |
1507 |
| - * [ ] [`_mm512_i32loextgather_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32loextgather_pd&expand=5236) |
1508 |
| - * [ ] [`_mm512_i32loextscatter_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32loextscatter_epi64&expand=5236) |
1509 |
| - * [ ] [`_mm512_i32loextscatter_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32loextscatter_pd&expand=5236) |
1510 |
| - * [ ] [`_mm512_i32logather_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32logather_epi64&expand=5236) |
1511 |
| - * [ ] [`_mm512_i32logather_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32logather_pd&expand=5236) |
1512 |
| - * [ ] [`_mm512_i32loscatter_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32loscatter_pd&expand=5236) |
1513 |
| - * [x] [`_mm512_i32scatter_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32scatter_epi32&expand=5236) |
1514 |
| - * [x] [`_mm512_i32scatter_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32scatter_epi64&expand=5236) |
1515 |
| - * [x] [`_mm512_i32scatter_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32scatter_pd&expand=5236) |
1516 |
| - * [x] [`_mm512_i32scatter_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32scatter_ps&expand=5236) |
1517 |
| - * [x] [`_mm512_i64gather_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i64gather_epi32&expand=5236) |
1518 |
| - * [x] [`_mm512_i64gather_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i64gather_epi64&expand=5236) |
1519 |
| - * [x] [`_mm512_i64gather_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i64gather_pd&expand=5236) |
1520 |
| - * [x] [`_mm512_i64gather_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i64gather_ps&expand=5236) |
1521 |
| - * [x] [`_mm512_i64scatter_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i64scatter_epi32&expand=5236) |
1522 |
| - * [x] [`_mm512_i64scatter_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i64scatter_epi64&expand=5236) |
1523 |
| - * [x] [`_mm512_i64scatter_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i64scatter_pd&expand=5236) |
1524 |
| - * [x] [`_mm512_i64scatter_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i64scatter_ps&expand=5236) |
1525 | 1654 | * [x] [`_mm512_insertf32x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_insertf32x4&expand=5236)
|
1526 | 1655 | * [x] [`_mm512_insertf64x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_insertf64x4&expand=5236)
|
1527 | 1656 | * [x] [`_mm512_inserti32x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_inserti32x4&expand=5236)
|
|
1642 | 1771 | * [x] [`_mm512_mask_extractf64x4_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_extractf64x4_pd&expand=5236)
|
1643 | 1772 | * [x] [`_mm512_mask_extracti32x4_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_extracti32x4_epi32&expand=5236)
|
1644 | 1773 | * [x] [`_mm512_mask_extracti64x4_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_extracti64x4_epi64&expand=5236)
|
1645 |
| - * [ ] [`_mm512_mask_i32extgather_epi32`] |
1646 |
| - * [ ] [`_mm512_mask_i32extgather_ps`] |
1647 |
| - * [ ] [`_mm512_mask_i32extscatter_epi32`] |
1648 |
| - * [ ] [`_mm512_mask_i32extscatter_ps`] |
1649 |
| - * [x] [`_mm512_mask_i32gather_epi32`] |
1650 |
| - * [x] [`_mm512_mask_i32gather_epi64`] |
1651 |
| - * [x] [`_mm512_mask_i32gather_pd`] |
1652 |
| - * [x] [`_mm512_mask_i32gather_ps`] |
1653 |
| - * [ ] [`_mm512_mask_i32loextgather_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i32loextgather_epi64&expand=5236) |
1654 |
| - * [ ] [`_mm512_mask_i32loextgather_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i32loextgather_pd&expand=5236) |
1655 |
| - * [ ] [`_mm512_mask_i32loextscatter_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i32loextscatter_epi64&expand=5236) |
1656 |
| - * [ ] [`_mm512_mask_i32loextscatter_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i32loextscatter_pd&expand=5236) |
1657 |
| - * [ ] [`_mm512_mask_i32logather_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i32logather_epi64&expand=5236) |
1658 |
| - * [ ] [`_mm512_mask_i32logather_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i32logather_pd&expand=5236) |
1659 |
| - * [ ] [`_mm512_mask_i32loscatter_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i32loscatter_pd&expand=5236) |
1660 |
| - * [x] [`_mm512_mask_i32scatter_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i32scatter_epi32&expand=5236) |
1661 |
| - * [x] [`_mm512_mask_i32scatter_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i32scatter_epi64&expand=5236) |
1662 |
| - * [x] [`_mm512_mask_i32scatter_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i32scatter_pd&expand=5236) |
1663 |
| - * [x] [`_mm512_mask_i32scatter_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i32scatter_ps&expand=5236) |
1664 |
| - * [x] [`_mm512_mask_i64gather_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i64gather_epi32&expand=5236) |
1665 |
| - * [x] [`_mm512_mask_i64gather_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i64gather_epi64&expand=5236) |
1666 |
| - * [x] [`_mm512_mask_i64gather_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i64gather_pd&expand=5236) |
1667 |
| - * [x] [`_mm512_mask_i64gather_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i64gather_ps&expand=5236) |
1668 |
| - * [x] [`_mm512_mask_i64scatter_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i64scatter_epi32&expand=5236) |
1669 |
| - * [x] [`_mm512_mask_i64scatter_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i64scatter_epi64&expand=5236) |
1670 |
| - * [x] [`_mm512_mask_i64scatter_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i64scatter_pd&expand=5236) |
1671 |
| - * [x] [`_mm512_mask_i64scatter_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i64scatter_ps&expand=5236) |
1672 | 1774 | * [x] [`_mm512_mask_insertf32x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_insertf32x4&expand=5236)
|
1673 | 1775 | * [x] [`_mm512_mask_insertf64x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_insertf64x4&expand=5236)
|
1674 | 1776 | * [x] [`_mm512_mask_inserti32x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_inserti32x4&expand=5236)
|
|
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