Skip to content

Commit 7f0a106

Browse files
dpaoliellodpaoliello
committed
arm64ec
1 parent 15b9572 commit 7f0a106

File tree

23 files changed

+572
-554
lines changed

23 files changed

+572
-554
lines changed

‎crates/core_arch/src/aarch64/neon/mod.rs

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -2074,7 +2074,7 @@ pub unsafe fn vget_low_p64(a: poly64x2_t) -> poly64x1_t {
20742074
#[target_feature(enable = "neon")]
20752075
#[rustc_legacy_const_generics(1)]
20762076
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2077-
#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(nop, IMM5 = 0))]
2077+
#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, IMM5 = 0))]
20782078
pub unsafe fn vget_lane_f64<const IMM5: i32>(v: float64x1_t) -> f64 {
20792079
static_assert!(IMM5 == 0);
20802080
simd_extract!(v, IMM5 as u32)
@@ -2085,7 +2085,7 @@ pub unsafe fn vget_lane_f64<const IMM5: i32>(v: float64x1_t) -> f64 {
20852085
#[target_feature(enable = "neon")]
20862086
#[rustc_legacy_const_generics(1)]
20872087
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2088-
#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(nop, IMM5 = 0))]
2088+
#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, IMM5 = 0))]
20892089
pub unsafe fn vgetq_lane_f64<const IMM5: i32>(v: float64x2_t) -> f64 {
20902090
static_assert_uimm_bits!(IMM5, 1);
20912091
simd_extract!(v, IMM5 as u32)
@@ -3417,7 +3417,7 @@ pub unsafe fn vsm3tt1aq_u32<const IMM2: i32>(
34173417
static_assert_uimm_bits!(IMM2, 2);
34183418
#[allow(improper_ctypes)]
34193419
extern "unadjusted" {
3420-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.sm3tt1a")]
3420+
#[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.sm3tt1a")]
34213421
fn vsm3tt1aq_u32_(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t, imm2: i64) -> uint32x4_t;
34223422
}
34233423
vsm3tt1aq_u32_(a, b, c, IMM2 as i64)
@@ -3437,7 +3437,7 @@ pub unsafe fn vsm3tt1bq_u32<const IMM2: i32>(
34373437
static_assert_uimm_bits!(IMM2, 2);
34383438
#[allow(improper_ctypes)]
34393439
extern "unadjusted" {
3440-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.sm3tt1b")]
3440+
#[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.sm3tt1b")]
34413441
fn vsm3tt1bq_u32_(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t, imm2: i64) -> uint32x4_t;
34423442
}
34433443
vsm3tt1bq_u32_(a, b, c, IMM2 as i64)
@@ -3457,7 +3457,7 @@ pub unsafe fn vsm3tt2aq_u32<const IMM2: i32>(
34573457
static_assert_uimm_bits!(IMM2, 2);
34583458
#[allow(improper_ctypes)]
34593459
extern "unadjusted" {
3460-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.sm3tt2a")]
3460+
#[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.sm3tt2a")]
34613461
fn vsm3tt2aq_u32_(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t, imm2: i64) -> uint32x4_t;
34623462
}
34633463
vsm3tt2aq_u32_(a, b, c, IMM2 as i64)
@@ -3477,7 +3477,7 @@ pub unsafe fn vsm3tt2bq_u32<const IMM2: i32>(
34773477
static_assert_uimm_bits!(IMM2, 2);
34783478
#[allow(improper_ctypes)]
34793479
extern "unadjusted" {
3480-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.sm3tt2b")]
3480+
#[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.sm3tt2b")]
34813481
fn vsm3tt2bq_u32_(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t, imm2: i64) -> uint32x4_t;
34823482
}
34833483
vsm3tt2bq_u32_(a, b, c, IMM2 as i64)
@@ -3493,7 +3493,7 @@ pub unsafe fn vxarq_u64<const IMM6: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64
34933493
static_assert_uimm_bits!(IMM6, 6);
34943494
#[allow(improper_ctypes)]
34953495
extern "unadjusted" {
3496-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.xar")]
3496+
#[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.xar")]
34973497
fn vxarq_u64_(a: uint64x2_t, b: uint64x2_t, n: i64) -> uint64x2_t;
34983498
}
34993499
vxarq_u64_(a, b, IMM6 as i64)

‎crates/core_arch/src/arm_shared/barrier/mod.rs

Lines changed: 12 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,7 @@
44
#[cfg(not(any(
55
// v8
66
target_arch = "aarch64",
7+
target_arch = "arm64ec",
78
// v7
89
target_feature = "v7",
910
// v6-M
@@ -13,6 +14,7 @@ mod cp15;
1314

1415
#[cfg(not(any(
1516
target_arch = "aarch64",
17+
target_arch = "arm64ec",
1618
target_feature = "v7",
1719
target_feature = "mclass"
1820
)))]
@@ -22,6 +24,7 @@ pub use self::cp15::*;
2224
// Dedicated instructions
2325
#[cfg(any(
2426
target_arch = "aarch64",
27+
target_arch = "arm64ec",
2528
target_feature = "v7",
2629
target_feature = "mclass"
2730
))]
@@ -47,30 +50,32 @@ macro_rules! dmb_dsb {
4750

4851
#[cfg(any(
4952
target_arch = "aarch64",
53+
target_arch = "arm64ec",
5054
target_feature = "v7",
5155
target_feature = "mclass"
5256
))]
5357
mod common;
5458

5559
#[cfg(any(
5660
target_arch = "aarch64",
61+
target_arch = "arm64ec",
5762
target_feature = "v7",
5863
target_feature = "mclass"
5964
))]
6065
#[unstable(feature = "stdarch_arm_barrier", issue = "117219")]
6166
pub use self::common::*;
6267

63-
#[cfg(any(target_arch = "aarch64", target_feature = "v7",))]
68+
#[cfg(any(target_arch = "aarch64", target_arch = "arm64ec",target_feature = "v7",))]
6469
mod not_mclass;
6570

66-
#[cfg(any(target_arch = "aarch64", target_feature = "v7",))]
71+
#[cfg(any(target_arch = "aarch64", target_arch = "arm64ec", target_feature = "v7",))]
6772
#[unstable(feature = "stdarch_arm_barrier", issue = "117219")]
6873
pub use self::not_mclass::*;
6974

70-
#[cfg(target_arch = "aarch64")]
75+
#[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
7176
mod v8;
7277

73-
#[cfg(target_arch = "aarch64")]
78+
#[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
7479
#[unstable(feature = "stdarch_arm_barrier", issue = "117219")]
7580
pub use self::v8::*;
7681

@@ -132,15 +137,15 @@ where
132137
}
133138

134139
extern "unadjusted" {
135-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.dmb")]
140+
#[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.dmb")]
136141
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.dmb")]
137142
fn dmb(_: i32);
138143

139-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.dsb")]
144+
#[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.dsb")]
140145
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.dsb")]
141146
fn dsb(_: i32);
142147

143-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.isb")]
148+
#[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.isb")]
144149
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.isb")]
145150
fn isb(_: i32);
146151
}

‎crates/core_arch/src/arm_shared/crc.rs

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1,26 +1,26 @@
11
extern "unadjusted" {
2-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crc32b")]
2+
#[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crc32b")]
33
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32b")]
44
fn crc32b_(crc: u32, data: u32) -> u32;
5-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crc32h")]
5+
#[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crc32h")]
66
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32h")]
77
fn crc32h_(crc: u32, data: u32) -> u32;
8-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crc32w")]
8+
#[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crc32w")]
99
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32w")]
1010
fn crc32w_(crc: u32, data: u32) -> u32;
1111

12-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crc32cb")]
12+
#[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crc32cb")]
1313
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32cb")]
1414
fn crc32cb_(crc: u32, data: u32) -> u32;
15-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crc32ch")]
15+
#[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crc32ch")]
1616
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32ch")]
1717
fn crc32ch_(crc: u32, data: u32) -> u32;
18-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crc32cw")]
18+
#[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crc32cw")]
1919
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32cw")]
2020
fn crc32cw_(crc: u32, data: u32) -> u32;
21-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crc32x")]
21+
#[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crc32x")]
2222
fn crc32x_(crc: u32, data: u64) -> u32;
23-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crc32cx")]
23+
#[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crc32cx")]
2424
fn crc32cx_(crc: u32, data: u64) -> u32;
2525
}
2626

@@ -104,7 +104,7 @@ pub unsafe fn __crc32cw(crc: u32, data: u32) -> u32 {
104104
/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32d)
105105
#[inline]
106106
#[target_feature(enable = "crc")]
107-
#[cfg(target_arch = "aarch64")]
107+
#[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
108108
#[cfg_attr(test, assert_instr(crc32x))]
109109
#[unstable(feature = "stdarch_arm_crc32", issue = "117215")]
110110
pub unsafe fn __crc32d(crc: u32, data: u64) -> u32 {
@@ -133,7 +133,7 @@ pub unsafe fn __crc32d(crc: u32, data: u64) -> u32 {
133133
/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cd)
134134
#[inline]
135135
#[target_feature(enable = "crc")]
136-
#[cfg(target_arch = "aarch64")]
136+
#[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
137137
#[cfg_attr(test, assert_instr(crc32cx))]
138138
#[unstable(feature = "stdarch_arm_crc32", issue = "117215")]
139139
pub unsafe fn __crc32cd(crc: u32, data: u64) -> u32 {

‎crates/core_arch/src/arm_shared/crypto.rs

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -2,48 +2,48 @@ use crate::core_arch::arm_shared::{uint32x4_t, uint8x16_t};
22

33
#[allow(improper_ctypes)]
44
extern "unadjusted" {
5-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.aese")]
5+
#[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.aese")]
66
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aese")]
77
fn vaeseq_u8_(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t;
8-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.aesd")]
8+
#[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.aesd")]
99
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aesd")]
1010
fn vaesdq_u8_(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t;
11-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.aesmc")]
11+
#[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.aesmc")]
1212
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aesmc")]
1313
fn vaesmcq_u8_(data: uint8x16_t) -> uint8x16_t;
14-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.aesimc")]
14+
#[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.aesimc")]
1515
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aesimc")]
1616
fn vaesimcq_u8_(data: uint8x16_t) -> uint8x16_t;
1717

18-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.sha1h")]
18+
#[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.sha1h")]
1919
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1h")]
2020
fn vsha1h_u32_(hash_e: u32) -> u32;
21-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.sha1su0")]
21+
#[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.sha1su0")]
2222
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1su0")]
2323
fn vsha1su0q_u32_(w0_3: uint32x4_t, w4_7: uint32x4_t, w8_11: uint32x4_t) -> uint32x4_t;
24-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.sha1su1")]
24+
#[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.sha1su1")]
2525
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1su1")]
2626
fn vsha1su1q_u32_(tw0_3: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t;
27-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.sha1c")]
27+
#[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.sha1c")]
2828
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1c")]
2929
fn vsha1cq_u32_(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t;
30-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.sha1p")]
30+
#[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.sha1p")]
3131
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1p")]
3232
fn vsha1pq_u32_(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t;
33-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.sha1m")]
33+
#[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.sha1m")]
3434
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1m")]
3535
fn vsha1mq_u32_(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t;
3636

37-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.sha256h")]
37+
#[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.sha256h")]
3838
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256h")]
3939
fn vsha256hq_u32_(hash_abcd: uint32x4_t, hash_efgh: uint32x4_t, wk: uint32x4_t) -> uint32x4_t;
40-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.sha256h2")]
40+
#[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.sha256h2")]
4141
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256h2")]
4242
fn vsha256h2q_u32_(hash_efgh: uint32x4_t, hash_abcd: uint32x4_t, wk: uint32x4_t) -> uint32x4_t;
43-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.sha256su0")]
43+
#[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.sha256su0")]
4444
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256su0")]
4545
fn vsha256su0q_u32_(w0_3: uint32x4_t, w4_7: uint32x4_t) -> uint32x4_t;
46-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.sha256su1")]
46+
#[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.sha256su1")]
4747
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256su1")]
4848
fn vsha256su1q_u32_(tw0_3: uint32x4_t, w8_11: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t;
4949
}

‎crates/core_arch/src/arm_shared/hints.rs

Lines changed: 8 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@
99
/// low-power state until one of a number of asynchronous events occurs.
1010
// Section 10.1 of ACLE says that the supported arches are: 8, 6K, 6-M
1111
// LLVM says "instruction requires: armv6k"
12-
#[cfg(any(target_feature = "v6", target_arch = "aarch64", doc))]
12+
#[cfg(any(target_feature = "v6", target_arch = "aarch64", target_arch = "arm64ec", doc))]
1313
#[inline(always)]
1414
#[unstable(feature = "stdarch_arm_hints", issue = "117218")]
1515
pub unsafe fn __wfi() {
@@ -23,7 +23,7 @@ pub unsafe fn __wfi() {
2323
/// another processor.
2424
// Section 10.1 of ACLE says that the supported arches are: 8, 6K, 6-M
2525
// LLVM says "instruction requires: armv6k"
26-
#[cfg(any(target_feature = "v6", target_arch = "aarch64", doc))]
26+
#[cfg(any(target_feature = "v6", target_arch = "aarch64", target_arch = "arm64ec", doc))]
2727
#[inline(always)]
2828
#[unstable(feature = "stdarch_arm_hints", issue = "117218")]
2929
pub unsafe fn __wfe() {
@@ -36,7 +36,7 @@ pub unsafe fn __wfe() {
3636
/// system. It is a NOP on a uniprocessor system.
3737
// Section 10.1 of ACLE says that the supported arches are: 8, 6K, 6-M, 7-M
3838
// LLVM says "instruction requires: armv6k"
39-
#[cfg(any(target_feature = "v6", target_arch = "aarch64", doc))]
39+
#[cfg(any(target_feature = "v6", target_arch = "aarch64", target_arch = "arm64ec", doc))]
4040
#[inline(always)]
4141
#[unstable(feature = "stdarch_arm_hints", issue = "117218")]
4242
pub unsafe fn __sev() {
@@ -52,6 +52,7 @@ pub unsafe fn __sev() {
5252
#[cfg(any(
5353
target_feature = "v8", // 32-bit ARMv8
5454
target_arch = "aarch64", // AArch64
55+
target_arch = "arm64ec", // Arm64EC
5556
doc,
5657
))]
5758
#[inline(always)]
@@ -67,7 +68,7 @@ pub unsafe fn __sevl() {
6768
/// improve overall system performance.
6869
// Section 10.1 of ACLE says that the supported arches are: 8, 6K, 6-M
6970
// LLVM says "instruction requires: armv6k"
70-
#[cfg(any(target_feature = "v6", target_arch = "aarch64", doc))]
71+
#[cfg(any(target_feature = "v6", target_arch = "aarch64", target_arch = "arm64ec", doc))]
7172
#[inline(always)]
7273
#[unstable(feature = "stdarch_arm_hints", issue = "117218")]
7374
pub unsafe fn __yield() {
@@ -80,14 +81,16 @@ pub unsafe fn __yield() {
8081
/// those that do, it is unspecified whether this intrinsic generates it or
8182
/// another instruction. It is not guaranteed that inserting this instruction
8283
/// will increase execution time.
84+
// Inline ASM is not support on ARM64EC yet.
85+
#[cfg(not(target_arch = "arm64ec"))]
8386
#[inline(always)]
8487
#[unstable(feature = "stdarch_arm_hints", issue = "117218")]
8588
pub unsafe fn __nop() {
8689
crate::arch::asm!("nop", options(nomem, nostack, preserves_flags));
8790
}
8891

8992
extern "unadjusted" {
90-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.hint")]
93+
#[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.hint")]
9194
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.hint")]
9295
fn hint(_: i32);
9396
}

‎crates/core_arch/src/arm_shared/mod.rs

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -66,11 +66,11 @@ pub use crc::*;
6666

6767
// NEON intrinsics are currently broken on big-endian, so don't expose them. (#1484)
6868
#[cfg(target_endian = "little")]
69-
#[cfg(any(target_arch = "aarch64", target_feature = "v7", doc))]
69+
#[cfg(any(target_arch = "aarch64", target_arch = "arm64ec", target_feature = "v7", doc))]
7070
mod crypto;
7171
// NEON intrinsics are currently broken on big-endian, so don't expose them. (#1484)
7272
#[cfg(target_endian = "little")]
73-
#[cfg(any(target_arch = "aarch64", target_feature = "v7", doc))]
73+
#[cfg(any(target_arch = "aarch64", target_arch = "arm64ec", target_feature = "v7", doc))]
7474
#[cfg_attr(
7575
target_arch = "arm",
7676
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
@@ -83,10 +83,10 @@ pub use self::crypto::*;
8383

8484
// NEON intrinsics are currently broken on big-endian, so don't expose them. (#1484)
8585
#[cfg(target_endian = "little")]
86-
#[cfg(any(target_arch = "aarch64", target_feature = "v7", doc))]
86+
#[cfg(any(target_arch = "aarch64", target_arch = "arm64ec", target_feature = "v7", doc))]
8787
pub(crate) mod neon;
8888
#[cfg(target_endian = "little")]
89-
#[cfg(any(target_arch = "aarch64", target_feature = "v7", doc))]
89+
#[cfg(any(target_arch = "aarch64", target_arch = "arm64ec", target_feature = "v7", doc))]
9090
#[cfg_attr(
9191
not(target_arch = "arm"),
9292
stable(feature = "neon_intrinsics", since = "1.59.0")
@@ -98,7 +98,7 @@ pub(crate) mod neon;
9898
pub use self::neon::*;
9999

100100
#[cfg(test)]
101-
#[cfg(any(target_arch = "aarch64", target_feature = "v7", doc))]
101+
#[cfg(any(target_arch = "aarch64", target_arch = "arm64ec", target_feature = "v7", doc))]
102102
pub(crate) mod test_support;
103103

104104
mod sealed {

‎crates/core_arch/src/arm_shared/neon/load_tests.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@ use super::*;
77
#[cfg(target_arch = "arm")]
88
use crate::core_arch::arm::*;
99

10-
#[cfg(target_arch = "aarch64")]
10+
#[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
1111
use crate::core_arch::aarch64::*;
1212

1313
use crate::core_arch::simd::*;

0 commit comments

Comments
 (0)