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Revert "std_detect: RISC-V platform guide documentation"
This reverts commit e907456. This is due to a CI failure (technically broken HTML with duplicate IDs) caused by this commit (visibly fine but invalid per the HTML specification and detected by the LinkCheck tool on the Rust CI process). The author independently working on a rustdoc enhancement to enable writing multiple references to a single footnote. If that change makes it to the stage0 compiler (next beta), the original change will be acceptable again (possibly targeting for the version 1.89).
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‎crates/std_detect/src/detect/arch/riscv.rs

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@@ -22,133 +22,87 @@ features! {
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///
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/// [ISA manual]: https://riscv.org/specifications/ratified/
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///
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/// # Platform-specific/agnostic Behavior and Availability
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///
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/// Runtime detection depends on the platform-specific feature detection
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/// facility and its availability per feature is
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/// highly platform/version-specific.
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///
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/// Still, a best-effort attempt is performed to enable subset/dependent
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/// features if a superset feature is enabled regardless of the platform.
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/// For instance, if the A extension (`"a"`) is enabled, its subsets (the
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/// Zalrsc and Zaamo extensions; `"zalrsc"` and `"zaamo"`) are also enabled.
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/// Likewise, if the F extension (`"f"`) is enabled, one of its dependencies
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/// (the Zicsr extension `"zicsr"`) is also enabled.
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///
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/// # Unprivileged Specification
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///
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/// The supported ratified RISC-V instruction sets are as follows (OS
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/// columns denote runtime feature detection support with or without the
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/// minimum supported version):
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///
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/// | Literal | Base | Linux |
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/// |:---------- |:------- |:---------- |
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/// | `"rv32e"` | RV32E | No |
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/// | `"rv32i"` | RV32I | Yes [^ima] |
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/// | `"rv64i"` | RV64I | Yes [^ima] |
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///
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/// | Literal | Extension | Linux |
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/// |:--------------- |:----------- |:------------------ |
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/// | `"a"` | A | Yes [^ima] |
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/// | `"b"` | B | 6.5 |
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/// | `"c"` | C | Yes |
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/// | `"d"` | D | Yes |
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/// | `"f"` | F | Yes |
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/// | `"m"` | M | Yes [^ima] |
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/// | `"q"` | Q | No |
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/// | `"v"` | V | 6.5 |
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/// | `"zaamo"` | Zaamo | No [^ima] [^dep] |
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/// | `"zacas"` | Zacas | 6.8 |
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/// | `"zalrsc"` | Zalrsc | No [^ima] [^dep] |
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/// | `"zawrs"` | Zawrs | 6.11 |
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/// | `"zba"` | Zba | 6.5 |
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/// | `"zbb"` | Zbb | 6.5 |
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/// | `"zbc"` | Zbc | 6.8 |
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/// | `"zbkb"` | Zbkb | 6.8 |
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/// | `"zbkc"` | Zbkc | 6.8 |
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/// | `"zbkx"` | Zbkx | 6.8 |
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/// | `"zbs"` | Zbs | 6.5 |
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/// | `"zca"` | Zca | 6.11 [^dep] |
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/// | `"zcb"` | Zcb | 6.11 [^dep] |
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/// | `"zcd"` | Zcd | 6.11 [^dep] |
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/// | `"zcf"` | Zcf | 6.11 [^dep] |
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/// | `"zcmop"` | Zcmop | 6.11 |
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/// | `"zdinx"` | Zdinx | No |
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/// | `"zfa"` | Zfa | 6.8 |
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/// | `"zfh"` | Zfh | 6.8 |
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/// | `"zfhmin"` | Zfhmin | 6.8 |
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/// | `"zfinx"` | Zfinx | No |
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/// | `"zhinx"` | Zhinx | No |
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/// | `"zhinxmin"` | Zhinxmin | No |
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/// | `"zicboz"` | Zicboz | 6.7 |
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/// | `"zicntr"` | Zicntr | No [^ima-cntr] [^cntr] |
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/// | `"zicond"` | Zicond | 6.8 |
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/// | `"zicsr"` | Zicsr | No [^ima] [^dep] |
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/// | `"zifencei"` | Zifencei | No [^ima] |
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/// | `"zihintntl"` | Zihintntl | 6.8 |
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/// | `"zihintpause"` | Zihintpause | 6.10 |
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/// | `"zihpm"` | Zihpm | No |
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/// | `"zimop"` | Zimop | 6.11 |
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/// | `"zk"` | Zk | No [^zkr] |
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/// | `"zkn"` | Zkn | 6.8 |
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/// | `"zknd"` | Zknd | 6.8 |
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/// | `"zkne"` | Zkne | 6.8 |
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/// | `"zknh"` | Zknh | 6.8 |
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/// | `"zkr"` | Zkr | No [^zkr] |
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/// | `"zks"` | Zks | 6.8 |
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/// | `"zksed"` | Zksed | 6.8 |
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/// | `"zksh"` | Zksh | 6.8 |
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/// | `"zkt"` | Zkt | 6.8 |
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/// | `"ztso"` | Ztso | 6.8 |
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/// | `"zvbb"` | Zvbb | 6.8 |
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/// | `"zvbc"` | Zvbc | 6.8 |
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/// | `"zve32f"` | Zve32f | 6.11 [^dep] |
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/// | `"zve32x"` | Zve32x | 6.11 [^dep] |
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/// | `"zve64d"` | Zve64d | 6.11 [^dep] |
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/// | `"zve64f"` | Zve64f | 6.11 [^dep] |
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/// | `"zve64x"` | Zve64x | 6.11 [^dep] |
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/// | `"zvfh"` | Zvfh | 6.8 |
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/// | `"zvfhmin"` | Zvfhmin | 6.8 |
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/// | `"zvkb"` | Zvkb | 6.8 |
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/// | `"zvkg"` | Zvkg | 6.8 |
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/// | `"zvkn"` | Zvkn | 6.8 |
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/// | `"zvknc"` | Zvknc | 6.8 |
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/// | `"zvkned"` | Zvkned | 6.8 |
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/// | `"zvkng"` | Zvkng | 6.8 |
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/// | `"zvknha"` | Zvknha | 6.8 |
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/// | `"zvknhb"` | Zvknhb | 6.8 |
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/// | `"zvks"` | Zvks | 6.8 |
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/// | `"zvksc"` | Zvksc | 6.8 |
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/// | `"zvksed"` | Zvksed | 6.8 |
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/// | `"zvksg"` | Zvksg | 6.8 |
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/// | `"zvksh"` | Zvksh | 6.8 |
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/// | `"zvkt"` | Zvkt | 6.8 |
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///
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/// [^ima]: Or enabled when the IMA base behavior is enabled on the Linux
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/// kernel version 6.4 or later (for bases, the only matching one -- either
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/// `"rv32i"` or `"rv64i"` -- is enabled).
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///
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/// [^ima-cntr]: If the IMA base behavior is enabled on the Linux kernel
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/// version 6.4 or later, the Zicntr extension should be also present.
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/// However, it seems that Linux does not guarantee its existence.
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///
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/// [^cntr]: Even if this extension is available, it does not necessarily
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/// mean all performance counters are accessible.
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/// For instance, the Linux kernel version 6.6 or later prohibits accesses
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/// to performance counters other than `time` (wall-clock) by default.
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/// Also beware that, even if performance counters like `cycle` and
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/// `instret` are accessible, their value can be unreliable (e.g. returning
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/// the constant value) under certain circumstances.
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///
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/// [^dep]: Or enabled as a dependency of another extension (a superset)
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/// even if runtime detection of this feature itself is not supported (as
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/// long as the runtime detection of the superset is supported).
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/// The supported ratified RISC-V instruction sets are as follows:
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///
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/// [^zkr]: Linux does not report existence of this extension even if
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/// supported by the hardware mainly because the `seed` CSR is normally
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/// inaccessible from the user mode.
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/// For the Zk extension features except this CSR, check existence of both
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/// `"zkn"` and `"zkt"` features instead.
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/// * RV32E: `"rv32e"`
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/// * RV32I: `"rv32i"`
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/// * RV64I: `"rv64i"`
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/// * A: `"a"`
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/// * Zaamo: `"zaamo"`
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/// * Zalrsc: `"zalrsc"`
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/// * B: `"b"`
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/// * Zba: `"zba"`
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/// * Zbb: `"zbb"`
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/// * Zbs: `"zbs"`
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/// * C: `"c"`
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/// * Zca: `"zca"`
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/// * Zcd: `"zcd"` (if D is enabled)
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/// * Zcf: `"zcf"` (if F is enabled on RV32)
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/// * D: `"d"`
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/// * F: `"f"`
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/// * M: `"m"`
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/// * Q: `"q"`
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/// * V: `"v"`
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/// * Zve32x: `"zve32x"`
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/// * Zve32f: `"zve32f"`
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/// * Zve64x: `"zve64x"`
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/// * Zve64f: `"zve64f"`
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/// * Zve64d: `"zve64d"`
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/// * Zicboz: `"zicboz"`
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/// * Zicntr: `"zicntr"`
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/// * Zicond: `"zicond"`
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/// * Zicsr: `"zicsr"`
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/// * Zifencei: `"zifencei"`
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/// * Zihintntl: `"zihintntl"`
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/// * Zihintpause: `"zihintpause"`
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/// * Zihpm: `"zihpm"`
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/// * Zimop: `"zimop"`
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/// * Zacas: `"zacas"`
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/// * Zawrs: `"zawrs"`
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/// * Zfa: `"zfa"`
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/// * Zfh: `"zfh"`
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/// * Zfhmin: `"zfhmin"`
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/// * Zfinx: `"zfinx"`
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/// * Zdinx: `"zdinx"`
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/// * Zhinx: `"zhinx"`
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/// * Zhinxmin: `"zhinxmin"`
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/// * Zcb: `"zcb"`
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/// * Zcmop: `"zcmop"`
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/// * Zbc: `"zbc"`
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/// * Zbkb: `"zbkb"`
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/// * Zbkc: `"zbkc"`
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/// * Zbkx: `"zbkx"`
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/// * Zk: `"zk"`
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/// * Zkn: `"zkn"`
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/// * Zknd: `"zknd"`
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/// * Zkne: `"zkne"`
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/// * Zknh: `"zknh"`
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/// * Zkr: `"zkr"`
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/// * Zks: `"zks"`
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/// * Zksed: `"zksed"`
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/// * Zksh: `"zksh"`
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/// * Zkt: `"zkt"`
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/// * Zvbb: `"zvbb"`
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/// * Zvbc: `"zvbc"`
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/// * Zvfh: `"zvfh"`
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/// * Zvfhmin: `"zvfhmin"`
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/// * Zvkb: `"zvkb"`
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/// * Zvkg: `"zvkg"`
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/// * Zvkn: `"zvkn"`
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/// * Zvkned: `"zvkned"`
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/// * Zvknha: `"zvknha"`
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/// * Zvknhb: `"zvknhb"`
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/// * Zvknc: `"zvknc"`
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/// * Zvkng: `"zvkng"`
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/// * Zvks: `"zvks"`
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/// * Zvksed: `"zvksed"`
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/// * Zvksh: `"zvksh"`
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/// * Zvksc: `"zvksc"`
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/// * Zvksg: `"zvksg"`
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/// * Zvkt: `"zvkt"`
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/// * Ztso: `"ztso"`
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///
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/// There's also bases and extensions marked as standard instruction set,
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/// but they are in frozen or draft state. These instruction sets are also
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/// corresponding unaligned memory access is reasonably fast.
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///
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/// * `"unaligned-scalar-mem"`
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/// * Runtime detection requires Linux kernel version 6.4 or later.
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/// * `"unaligned-vector-mem"`
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/// * Runtime detection requires Linux kernel version 6.13 or later.
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#[stable(feature = "riscv_ratified", since = "1.78.0")]
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv32i: "rv32i";

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