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1 parent 07959ec commit 05a544eCopy full SHA for 05a544e
src/capability/msix.rs
@@ -39,6 +39,18 @@ impl MsixCapability {
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}
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+ /// Enable/disable masking of all interrupts for this PCI function.
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+ ///
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+ /// Individual interrupt sources can be masked using mask field of the corresponding entry in
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+ /// the MSI-X table.
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+ pub fn set_function_mask(&mut self, mask: bool, access: impl ConfigRegionAccess) {
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+ let mut control = unsafe { access.read(self.address.address, self.address.offset) };
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+ control.set_bit(30, mask);
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+ unsafe {
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+ access.write(self.address.address, self.address.offset, control);
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+ }
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+
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/// The index of the BAR that contains the MSI-X table.
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pub fn table_bar(&self) -> u8 {
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self.table.get_bits(0..3) as u8
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