@@ -113,31 +113,40 @@ impl MsiCapability {
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MultipleMessageSupport :: try_from ( reg. get_bits ( 4 ..7 ) as u8 ) . unwrap_or ( MultipleMessageSupport :: Int1 )
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}
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- /// Set the memory address that will be written to when the interrupt fires.
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+ /// Set the memory address that will be written to when the interrupt fires, and the data that
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+ /// will be written to it.
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+ pub fn set_message_info ( & self , address : u64 , data : u32 , access : impl ConfigRegionAccess ) {
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+ unsafe {
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+ access. write ( self . address . address , self . address . offset + 0x04 , address. get_bits ( 0 ..32 ) as u32 ) ;
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+ if self . is_64bit {
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+ access. write ( self . address . address , self . address . offset + 0x08 , address. get_bits ( 32 ..64 ) as u32 ) ;
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+ }
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+ }
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+ let data_offset = if self . is_64bit { 0x0c } else { 0x08 } ;
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+ unsafe {
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+ access. write ( self . address . address , self . address . offset + data_offset, data) ;
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+ }
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+ }
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+
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+ /// Set the memory address that will be written to when the interrupt fires, and the data that
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+ /// will be written to it, specialised for the message format the LAPIC expects.
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///
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/// # Arguments
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/// * `address` - Target Local APIC address (if not changed, can be calculated with `0xfee00000 | (processor << 12)`)
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/// * `vector` - Which interrupt vector should be triggered on LAPIC
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/// * `trigger_mode` - When interrupt should be triggered
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/// * `access` - PCI Configuration Space accessor
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- pub fn set_message_info (
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+ pub fn set_message_info_lapic (
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& self ,
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address : u64 ,
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vector : u8 ,
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trigger_mode : TriggerMode ,
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access : impl ConfigRegionAccess ,
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) {
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- unsafe {
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- access. write ( self . address . address , self . address . offset + 0x04 , address. get_bits ( 0 ..32 ) as u32 ) ;
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- if self . is_64bit {
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- access. write ( self . address . address , self . address . offset + 0x08 , address. get_bits ( 32 ..64 ) as u32 ) ;
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- }
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- }
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- let data_offset = if self . is_64bit { 0x0c } else { 0x08 } ;
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- let mut data = unsafe { access. read ( self . address . address , self . address . offset + data_offset) } ;
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+ let mut data = 0 ;
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data. set_bits ( 0 ..8 , vector as u32 ) ;
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data. set_bits ( 14 ..16 , trigger_mode as u32 ) ;
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- unsafe { access . write ( self . address . address , self . address . offset + data_offset , data ) }
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+ self . set_message_info ( address, data , access ) ;
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}
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/// Get interrupt mask
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