From 1c97c6f839dd07135769a1280e87789eed667ebb Mon Sep 17 00:00:00 2001 From: xuejun-xj Date: Mon, 19 Jun 2023 15:34:37 +0800 Subject: [PATCH 1/2] arm64: add KVM_REG_ARM64_SVE_VLS const For using SVE scenario, KVM_REG_ARM64_SVE_VLS is used by set_one_reg/get_one_reg ioctls, which allows the set of vector lengths supported by the vcpu to be discovered and configured by userspace. See https://www.kernel.org/doc/html/latest/virt/kvm/api.html#kvm-set-one-reg When using bindgen, this const is missing, so add it according to the definition in linux. Signed-off-by: xuejun-xj --- src/arm64/bindings.rs | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/arm64/bindings.rs b/src/arm64/bindings.rs index 1e7e6e2..5174322 100644 --- a/src/arm64/bindings.rs +++ b/src/arm64/bindings.rs @@ -285,6 +285,8 @@ pub const KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_NOT_AVAIL: u32 = 0; pub const KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_AVAIL: u32 = 1; pub const KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_NOT_REQUIRED: u32 = 2; pub const KVM_REG_ARM64_SVE: u32 = 1376256; +pub const KVM_REG_ARM64_SVE_VLS: u64 = + KVM_REG_ARM64 | KVM_REG_ARM64_SVE as u64 | KVM_REG_SIZE_U512 | 0xffff; pub const KVM_REG_ARM64_SVE_ZREG_BASE: u32 = 0; pub const KVM_REG_ARM64_SVE_PREG_BASE: u32 = 1024; pub const KVM_REG_ARM64_SVE_FFR_BASE: u32 = 1536; From 19520446bf9ec98b2b2043cf77023f0bf091c4bf Mon Sep 17 00:00:00 2001 From: xuejun-xj Date: Wed, 2 Aug 2023 19:50:08 +0800 Subject: [PATCH 2/2] CHANGELOG.md: update for PR #89 arm64: add KVM_REG_ARM64_SVE_VLS const Signed-off-by: xuejun-xj --- CHANGELOG.md | 1 + 1 file changed, 1 insertion(+) diff --git a/CHANGELOG.md b/CHANGELOG.md index 667c766..4cfd913 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,6 +1,7 @@ # Changelog ## [Unreleased] +- arm64: add KVM_REG_ARM64_SVE_VLS const - API change in the bindings from upstream kernel changes: * system_event has been made into a new union - The x86 module has been renamed to x86_64 for consistency (matches the kernel