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Copy file name to clipboardExpand all lines: doc/02_user/system_requirements.rst
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@@ -18,6 +18,10 @@ Please `file an issue <https://github.com/lowRISC/ibex/issues>`_ if you experien
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To run the UVM testbench a RTL simulator which supports SystemVerilog and UVM 1.2 is required.
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The `documentation of riscv-dv <https://github.com/google/riscv-dv#prerequisites>`_ contains a list of supported simulators.
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To compile code that runs on Ibex, you'll need a RISC-V toolchain.
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This isn't part of the core as such, but is necessary for verification.
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See the :doc:`Verification <../03_reference/verification>` section of the Reference Guide for more details about which toolchains the project currently uses for testing.
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