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Update google_riscv-dv to chipsalliance/riscv-dv@59dcd8c
Update code from upstream repository https://github.com/google/riscv- dv to revision 59dcd8c813484eb6dcca67e7e36089fe772b9cc8 * Update scripts for Metrics CI regression: bug fixes, change ISS to spike in CI regression (Aimee Sutton) * Add illegal and load store instruction (aneels3) * Avoid generating hint instruction when RV32C is turned off (chipsalliance/riscv-dv#787) (taoliug) * Fix illegal opcode issue in the cov_test (chipsalliance/riscv-dv#786) (taoliug) * [questa] Remove -access=rwc from vlog command line arguments (Rupert Swarbrick) * [ci] temporarily disable CI flow (Udi Jonnalagadda) * fix issue with rcs for num_of_harts (aneels3) * fix multi-hart label issue (aneels3) * add multi_hart test (ishita71) * Fix minor issues (aneels3) * Add riscv_signature_pkg (aneels3) * add gen_signature_handshake (ishita71) * Add gen_interrupt_vector_table (aneels3) * Remove the unnecessary lines (Anil Sharma) * fix issue with riscv_rand_instr_test (aneels3) * Add multiprocessing code block (aneels3) Signed-off-by: Rupert Swarbrick <[email protected]>
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‎vendor/google_riscv-dv.lock.hjson

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@@ -9,6 +9,6 @@
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upstream:
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{
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url: https://github.com/google/riscv-dv
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rev: 0b625258549e733082c12e5dc749f05aefb07d5a
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rev: 59dcd8c813484eb6dcca67e7e36089fe772b9cc8
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}
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}

‎vendor/google_riscv-dv/.github/workflows/metrics-regress.yml

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@@ -7,8 +7,8 @@ name: metrics-regress
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on:
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push:
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branches: [ master ]
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pull_request:
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branches: [ master ]
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# pull_request_target:
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# branches: [ master ]
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# If you fork this repository, you must create a new Metrics project for your fork
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# and set the environment variable $METRICS_PROJECT_ID accordingly
@@ -22,5 +22,6 @@ jobs:
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METRICS_CI_TOKEN: ${{ secrets.METRICS_CI_TOKEN }}
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METRICS_REGRESSION_NAME: riscv-dv_regression
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METRICS_PROJECT_ID: ${{ secrets.METRICS_PROJECT_ID }}
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PR_NUMBER: ${{ github.event.pull_request.number }}
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shell: bash
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‎vendor/google_riscv-dv/.metrics.json

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@@ -1,15 +1,8 @@
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{
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"variables": {
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"DSIM" : "${DSIM_HOME}/bin/dsim",
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"DSIM_LIB_PATH" : "${DSIM_HOME}/uvm-1.2/src/dpi",
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"RISCV_GCC" : "${RISCV_TOOLCHAIN}/bin/riscv-none-embed-gcc",
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"RISCV_OBJCOPY" : "${RISCV_TOOLCHAIN}/bin/riscv-none-embed-objcopy",
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"OVPSIM_PATH" : "/customer-tools/riscv-ovpsim/bin/Linux64"
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},
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"builds": {
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"list": [{
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"name": "rv32imc",
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"image": "ibex-dsim-toolchain:latest",
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"image": "ibex-toolchain:v2",
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"memory" : "1",
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"cmd": "python3 run.py --test riscv_arithmetic_basic_test --simulator dsim --output out --verbose --co",
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"wavesCmd": "python3 run.py --test riscv_arithmetic_basic_test --simulator dsim --output out --verbose --co"
@@ -27,8 +20,8 @@
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"name": "riscv_arithmetic_basic_test",
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"build": "rv32imc",
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"iterations": 2,
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"cmd": "cd /mux-flow/results; python3 <rootDir>/run.py --test riscv_arithmetic_basic_test --seed <seed> --simulator dsim --iss ovpsim --so --out <rootDir>/out --verbose; <rootDir>/scripts/check-status $?; rm -fr <rootDir>/out/dsim",
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"wavesCmd": "python3 <rootDir>/run.py --test riscv_arithmetic_basic_test --seed <seed> --simulator dsim --iss ovpsim --so --out <rootDir>/out --verbose; <rootDir>/scripts/check-status $?; rm -rf out/dsim",
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"cmd": "cd /mux-flow/results; python3 <rootDir>/run.py --test riscv_arithmetic_basic_test --seed <seed> --simulator dsim --iss spike --so --out <rootDir>/out --verbose; <rootDir>/scripts/check-status $?; rm -fr <rootDir>/out/dsim",
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"wavesCmd": "python3 <rootDir>/run.py --test riscv_arithmetic_basic_test --seed <seed> --simulator dsim --iss spike --so --out <rootDir>/out --verbose; <rootDir>/scripts/check-status $?; rm -rf out/dsim",
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"logFile": "simulation.log",
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"metricsFile": "metrics.db",
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"isPass": "Test passed",

‎vendor/google_riscv-dv/pygen/pygen_src/isa/riscv_compressed_instr.py

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@@ -30,55 +30,55 @@ def __init__(self):
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@vsc.constraint
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def rvc_csr_c(self):
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# Registers specified by the three-bit rs1’, rs2’, and rd’
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with vsc.implies(self.format.inside(vsc.rangelist(riscv_instr_format_t.CIW_FORMAT,
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# Registers specified by the three-bit rs1, rs2, and rd
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with vsc.if_then(self.format.inside(vsc.rangelist(riscv_instr_format_t.CIW_FORMAT,
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riscv_instr_format_t.CL_FORMAT,
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riscv_instr_format_t.CS_FORMAT,
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riscv_instr_format_t.CB_FORMAT,
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riscv_instr_format_t.CA_FORMAT))):
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with vsc.implies(self.has_rs1 == 1):
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with vsc.if_then(self.has_rs1 == 1):
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self.rs1.inside(vsc.rangelist(riscv_reg_t.S0, riscv_reg_t.S1, riscv_reg_t.A0,
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riscv_reg_t.A1, riscv_reg_t.A2, riscv_reg_t.A3,
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riscv_reg_t.A4, riscv_reg_t.A5))
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with vsc.implies(self.has_rs2 == 1):
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with vsc.if_then(self.has_rs2 == 1):
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self.rs2.inside(vsc.rangelist(riscv_reg_t.S0, riscv_reg_t.S1, riscv_reg_t.A0,
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riscv_reg_t.A1, riscv_reg_t.A2, riscv_reg_t.A3,
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riscv_reg_t.A4, riscv_reg_t.A5))
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with vsc.implies(self.has_rd == 1):
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with vsc.if_then(self.has_rd == 1):
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self.rd.inside(vsc.rangelist(riscv_reg_t.S0, riscv_reg_t.S1, riscv_reg_t.A0,
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riscv_reg_t.A1, riscv_reg_t.A2, riscv_reg_t.A3,
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riscv_reg_t.A4, riscv_reg_t.A5))
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# _ADDI16SP is only valid when rd == SP
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with vsc.implies(self.instr_name == riscv_instr_name_t.C_ADDI16SP):
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with vsc.if_then(self.instr_name == riscv_instr_name_t.C_ADDI16SP):
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self.rd == riscv_reg_t.SP
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with vsc.implies(self.instr_name.inside(vsc.rangelist(riscv_instr_name_t.C_JR,
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with vsc.if_then(self.instr_name.inside(vsc.rangelist(riscv_instr_name_t.C_JR,
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riscv_instr_name_t.C_JALR))):
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self.rs1 != riscv_reg_t.ZERO
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self.rs2 == riscv_reg_t.ZERO
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@vsc.constraint
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def imm_val_c(self):
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with vsc.implies(self.imm_type.inside(vsc.rangelist(imm_t.NZIMM, imm_t.NZUIMM))):
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with vsc.if_then(self.imm_type.inside(vsc.rangelist(imm_t.NZIMM, imm_t.NZUIMM))):
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self.imm[5:0] != 0
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with vsc.implies(self.instr_name == riscv_instr_name_t.C_LUI):
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with vsc.if_then(self.instr_name == riscv_instr_name_t.C_LUI):
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self.imm[31:5] == 0
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with vsc.implies(self.instr_name.inside(vsc.rangelist(riscv_instr_name_t.C_SRAI,
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with vsc.if_then(self.instr_name.inside(vsc.rangelist(riscv_instr_name_t.C_SRAI,
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riscv_instr_name_t.C_SRLI,
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riscv_instr_name_t.C_SLLI))):
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self.imm[31:5] == 0
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with vsc.implies(self.instr_name == riscv_instr_name_t.C_ADDI4SPN):
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with vsc.if_then(self.instr_name == riscv_instr_name_t.C_ADDI4SPN):
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self.imm[1:0] == 0
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# C_JAL is RV32C only instruction
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@vsc.constraint
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def jal_c(self):
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with vsc.implies(self.XLEN != 32):
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with vsc.if_then(self.XLEN != 32):
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self.instr_name != riscv_instr_name_t.C_JAL
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# Avoid generating HINT or illegal instruction by default as it's not supported by the compiler
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@vsc.constraint
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def no_hint_illegal_instr_c(self):
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with vsc.implies(self.instr_name.inside(vsc.rangelist(riscv_instr_name_t.C_ADDI,
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with vsc.if_then(self.instr_name.inside(vsc.rangelist(riscv_instr_name_t.C_ADDI,
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riscv_instr_name_t.C_ADDIW,
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riscv_instr_name_t.C_LI,
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riscv_instr_name_t.C_LUI,
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riscv_instr_name_t.C_ADD,
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riscv_instr_name_t.C_LWSP))):
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self.rd != riscv_reg_t.ZERO
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with vsc.implies(self.instr_name == riscv_instr_name_t.C_JR):
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with vsc.if_then(self.instr_name == riscv_instr_name_t.C_JR):
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self.rs1 != riscv_reg_t.ZERO
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with vsc.implies(self.instr_name.inside(vsc.rangelist(riscv_instr_name_t.C_ADD,
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with vsc.if_then(self.instr_name.inside(vsc.rangelist(riscv_instr_name_t.C_ADD,
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riscv_instr_name_t.C_MV))):
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self.rs2 != riscv_reg_t.ZERO
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with vsc.implies(self.instr_name == riscv_instr_name_t.C_LUI):
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with vsc.if_then(self.instr_name == riscv_instr_name_t.C_LUI):
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self.rd != riscv_reg_t.SP
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def set_imm_len(self):

‎vendor/google_riscv-dv/pygen/pygen_src/isa/riscv_instr.py

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@vsc.constraint
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def imm_c(self):
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with vsc.implies(self.instr_name.inside(vsc.rangelist(riscv_instr_name_t.SLLIW,
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with vsc.if_then(self.instr_name.inside(vsc.rangelist(riscv_instr_name_t.SLLIW,
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riscv_instr_name_t.SRLIW,
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riscv_instr_name_t.SRAIW))):
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self.imm[11:5] == 0
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with vsc.implies(self.instr_name.inside(vsc.rangelist(riscv_instr_name_t.SLLI,
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with vsc.if_then(self.instr_name.inside(vsc.rangelist(riscv_instr_name_t.SLLI,
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riscv_instr_name_t.SRLI,
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riscv_instr_name_t.SRAI))):
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with vsc.implies(self.XLEN == 32):
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with vsc.if_then(self.XLEN == 32):
109109
self.imm[11:5] == 0
110-
with vsc.implies(self.XLEN != 32):
110+
with vsc.if_then(self.XLEN != 32):
111111
self.imm[11:6] == 0
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@classmethod

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