Fixes for stm32-rs/stm32g4xx-hal#34

Author: richardeoin

src/filter.rs

@@ -37,7 +37,7 @@ impl StandardFilter {
                 filter: 0x0,
                 mask: 0x0,
             },
-            action: Action::StoreInFifo0,
+            action: Action::StoreInFifo1,
         }
     }
 
@@ -80,7 +80,7 @@ impl ExtendedFilter {
                 filter: 0x0,
                 mask: 0x0,
             },
-            action: Action::StoreInFifo0,
+            action: Action::StoreInFifo1,
         }
     }
 

src/lib.rs

@@ -1356,7 +1356,7 @@ where
         // Check if there is a request pending to abort
         if self.has_pending_frame(idx) {
             let idx: u8 = idx.into();
-            let idx: u32 = idx as u32;
+            let idx: u32 = 1u32 << (idx as u32);
 
             // Abort Request
             can.txbcr.write(|w| unsafe { w.cr().bits(idx) });
@@ -1377,7 +1377,7 @@ where
     fn has_pending_frame(&self, idx: Mailbox) -> bool {
         let can = self.registers();
         let idx: u8 = idx.into();
-        let idx: u32 = idx as u32;
+        let idx: u32 = 1u32 << (idx as u32);
 
         can.txbrp.read().trp().bits() & idx != 0
     }

src/message_ram/txbuffer_element.rs

@@ -137,7 +137,7 @@ impl<'a> ID_W<'a> {
     #[allow(dead_code)]
     pub unsafe fn bits(self, value: u32) -> &'a mut W {
         self.w.bits[0] =
-            (self.w.bits[0] & !(0x0FFFFFFF)) | ((value as u32) & 0x0FFFFFFF);
+            (self.w.bits[0] & !(0x1FFFFFFF)) | ((value as u32) & 0x1FFFFFFF);
         self.w
     }
 }