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Rename message RAM instance export
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2 files changed

+10
-8
lines changed

2 files changed

+10
-8
lines changed

src/lib.rs

Lines changed: 9 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -24,9 +24,7 @@
2424
#[allow(clippy::all)] // generated code
2525
mod pac;
2626
use self::pac::generic::*; // To make the PAC extraction build
27-
28-
//#[allow(clippy::all)] // generated code
29-
mod message_ram;
27+
pub use crate::pac::fdcan::RegisterBlock;
3028

3129
/// Configuration of an FDCAN instance
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pub mod config;
@@ -40,6 +38,8 @@ pub mod frame;
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pub mod id;
4139
/// Interrupt Line Information
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pub mod interrupt;
41+
/// Message RAM block
42+
pub mod message_ram;
4343

4444
mod sealed {
4545
pub trait Sealed {}
@@ -58,9 +58,6 @@ use frame::{RxFrameInfo, TxFrameHeader};
5858
use id::{Id, IdReg};
5959
use interrupt::{Interrupt, InterruptLine, Interrupts};
6060

61-
use pac::fdcan::RegisterBlock;
62-
63-
use message_ram::MsgRamExt;
6461
use message_ram::RxFifoElement;
6562

6663
use core::cmp::Ord;
@@ -82,7 +79,7 @@ use core::ptr::NonNull;
8279
/// register block.
8380
/// * `REGISTERS` is a pointer to that peripheral's register block and can be safely accessed for as
8481
/// long as ownership or a borrow of the implementing type is present.
85-
pub unsafe trait Instance: MsgRamExt {
82+
pub unsafe trait Instance: message_ram::Instance {
8683
/// Pointer to the instance's register block.
8784
const REGISTERS: *mut RegisterBlock;
8885
}
@@ -522,6 +519,11 @@ impl<I> FdCan<I, PoweredDownMode>
522519
where
523520
I: Instance,
524521
{
522+
/// Creates a [`FdCan`] interface with the default configuration
523+
pub fn new(instance: I) -> Self {
524+
Self::create_can(FdCanConfig::default(), instance)
525+
}
526+
525527
/// Moves out of PoweredDownMode and into ConfigMode
526528
#[inline]
527529
pub fn into_config_mode(mut self) -> FdCan<I, ConfigMode> {

src/message_ram.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -144,7 +144,7 @@ impl generic::Writable for TxBufferElementHeader {}
144144
/// other accesses to the register block.
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/// * `MSG_RAM` is a pointer to the Message RAM block and can be safely accessed
146146
/// for as long as ownership or a borrow of the implementing type is present.
147-
pub unsafe trait MsgRamExt {
147+
pub unsafe trait Instance {
148148
const MSG_RAM: *mut RegisterBlock;
149149
fn msg_ram(&self) -> &RegisterBlock {
150150
unsafe { &*Self::MSG_RAM }

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