diff --git a/src/i2c.rs b/src/i2c.rs
index 60c738e..d7e33d4 100644
--- a/src/i2c.rs
+++ b/src/i2c.rs
@@ -17,134 +17,6 @@ pub struct I2c<I2C, SCLPIN, SDAPIN> {
 pub trait SclPin<I2C> {}
 pub trait SdaPin<I2C> {}
 
-macro_rules! i2c_pins {
-    ($($I2C:ident => {
-        scl => [$($scl:ty),+ $(,)*],
-        sda => [$($sda:ty),+ $(,)*],
-    })+) => {
-        $(
-            $(
-                impl SclPin<crate::stm32::$I2C> for $scl {}
-            )+
-            $(
-                impl SdaPin<crate::stm32::$I2C> for $sda {}
-            )+
-        )+
-    }
-}
-
-#[cfg(any(
-    feature = "stm32f030",
-    feature = "stm32f031",
-    feature = "stm32f038",
-    feature = "stm32f042",
-    feature = "stm32f048",
-    feature = "stm32f051",
-    feature = "stm32f058",
-    feature = "stm32f070",
-    feature = "stm32f071",
-    feature = "stm32f072",
-    feature = "stm32f078",
-    feature = "stm32f091",
-    feature = "stm32f098",
-))]
-i2c_pins! {
-    I2C1 => {
-        scl => [gpiob::PB6<Alternate<AF1>>, gpiob::PB8<Alternate<AF1>>],
-        sda => [gpiob::PB7<Alternate<AF1>>, gpiob::PB9<Alternate<AF1>>],
-    }
-}
-#[cfg(any(
-    feature = "stm32f030x4",
-    feature = "stm32f030x6",
-    feature = "stm32f030xc",
-    feature = "stm32f031",
-    feature = "stm32f038",
-    feature = "stm32f042",
-    feature = "stm32f048",
-    feature = "stm32f070x6",
-    feature = "stm32f091",
-    feature = "stm32f098",
-))]
-i2c_pins! {
-    I2C1 => {
-        scl => [gpioa::PA9<Alternate<AF4>>],
-        sda => [gpioa::PA10<Alternate<AF4>>],
-    }
-}
-#[cfg(any(feature = "stm32f030", feature = "stm32f042", feature = "stm32f048"))]
-i2c_pins! {
-    I2C1 => {
-        scl => [gpioa::PA11<Alternate<AF5>>],
-        sda => [gpioa::PA12<Alternate<AF5>>],
-    }
-}
-#[cfg(any(
-    feature = "stm32f030x4",
-    feature = "stm32f030x6",
-    feature = "stm32f031",
-    feature = "stm32f038",
-    feature = "stm32f042",
-    feature = "stm32f048",
-))]
-i2c_pins! {
-    I2C1 => {
-        scl => [gpiob::PB10<Alternate<AF1>>],
-        sda => [gpiob::PB11<Alternate<AF1>>],
-    }
-}
-#[cfg(any(feature = "stm32f030xc", feature = "stm32f042", feature = "stm32f048"))]
-i2c_pins! {
-    I2C1 => {
-        scl => [gpiob::PB13<Alternate<AF5>>],
-        sda => [gpiob::PB14<Alternate<AF5>>],
-    }
-}
-#[cfg(any(
-    feature = "stm32f030xc",
-    feature = "stm32f042",
-    feature = "stm32f048",
-    feature = "stm32f070x6",
-    feature = "stm32f091",
-    feature = "stm32f098",
-))]
-i2c_pins! {
-    I2C1 => {
-        scl => [gpiof::PF1<Alternate<AF1>>],
-        sda => [gpiof::PF0<Alternate<AF1>>],
-    }
-}
-
-#[cfg(any(feature = "stm32f030x8", feature = "stm32f051", feature = "stm32f058"))]
-i2c_pins! {
-    I2C2 => {
-        scl => [gpiob::PB10<Alternate<AF1>>],
-        sda => [gpiob::PB11<Alternate<AF1>>],
-    }
-}
-#[cfg(any(
-    feature = "stm32f030xc",
-    feature = "stm32f070xb",
-    feature = "stm32f071",
-    feature = "stm32f072",
-    feature = "stm32f078",
-    feature = "stm32f091",
-    feature = "stm32f098",
-))]
-i2c_pins! {
-    I2C2 => {
-        scl => [gpiob::PB10<Alternate<AF1>>, gpiob::PB13<Alternate<AF5>>],
-        sda => [gpiob::PB11<Alternate<AF1>>, gpiob::PB14<Alternate<AF5>>],
-    }
-}
-#[cfg(any(feature = "stm32f091", feature = "stm32f098"))]
-i2c_pins! {
-    I2C2 => {
-        scl => [gpioa::PA11<Alternate<AF5>>],
-        sda => [gpioa::PA12<Alternate<AF5>>],
-    }
-}
-
 #[derive(Debug)]
 pub enum Error {
     OVERRUN,
diff --git a/src/lib.rs b/src/lib.rs
index 510e1b4..e616ecc 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -35,6 +35,8 @@ pub mod gpio;
 #[cfg(feature = "device-selected")]
 pub mod i2c;
 #[cfg(feature = "device-selected")]
+pub mod pin_mappings;
+#[cfg(feature = "device-selected")]
 pub mod prelude;
 #[cfg(feature = "device-selected")]
 pub mod rcc;
diff --git a/src/pin_mappings.rs b/src/pin_mappings.rs
new file mode 100644
index 0000000..1ea75e3
--- /dev/null
+++ b/src/pin_mappings.rs
@@ -0,0 +1,187 @@
+#[cfg(feature = "device-selected")]
+use crate::gpio::gpioa::*;
+#[cfg(feature = "device-selected")]
+use crate::gpio::gpiob::*;
+#[allow(unused)]
+#[cfg(feature = "device-selected")]
+use crate::gpio::gpioc::*;
+#[cfg(feature = "stm32f030")]
+use crate::gpio::gpiod::*;
+#[allow(unused)]
+#[cfg(feature = "device-selected")]
+use crate::gpio::gpiof::*;
+#[allow(unused)]
+use crate::gpio::{Alternate, AF0, AF1, AF2, AF4, AF5};
+use crate::i2c::*;
+use crate::serial::*;
+use crate::spi::*;
+#[cfg(feature = "device-selected")]
+use crate::stm32::*;
+
+macro_rules! pins {
+    ($($PIN:ident => {
+        $($AF:ty: $TRAIT:ty),+
+    }),+) => {
+        $(
+            $(
+                impl $TRAIT for $PIN<Alternate<$AF>> {}
+            )+
+        )+
+    }
+}
+
+#[cfg(feature = "device-selected")]
+pins! {
+    PA5 => {AF0: SckPin<SPI1>},
+    PA6 => {AF0: MisoPin<SPI1>},
+    PA7 => {AF0: MosiPin<SPI1>},
+    PA9 => {AF1: TxPin<USART1>},
+    PA10 => {AF1: RxPin<USART1>},
+    PB3 => {AF0: SckPin<SPI1>},
+    PB4 => {AF0: MisoPin<SPI1>},
+    PB5 => {AF0: MosiPin<SPI1>},
+    PB6 => {
+        AF0: TxPin<USART1>,
+        AF1: SclPin<I2C1>
+    },
+    PB7 => {
+        AF0: RxPin<USART1>,
+        AF1: SdaPin<I2C1>
+    },
+    PB8 => {AF1: SclPin<I2C1>},
+    PB9 => {AF1: SdaPin<I2C1>}
+}
+
+#[cfg(feature = "stm32f030")]
+pins! {
+    PA0 => {AF4: TxPin<USART4>},
+    PA1 => {AF4: RxPin<USART4>},
+    PA4 => {AF5: TxPin<USART6>},
+    PA5 => {AF5: RxPin<USART6>},
+    PA11 => {AF5: SclPin<I2C1>},
+    PA12 => {AF5: SdaPin<I2C1>},
+    PB3 => {AF4: TxPin<USART5>},
+    PB4 => {AF4: RxPin<USART5>},
+    PB10 => {
+        AF4: TxPin<USART3>,
+        AF5: SckPin<SPI2>
+    },
+    PB11 => {AF4: RxPin<USART3>},
+    PC2 => {AF1: MisoPin<SPI2>},
+    PC3 => {AF1: MosiPin<SPI2>},
+    PC4 => {AF1: TxPin<USART3>},
+    PC5 => {AF1: RxPin<USART3>},
+    PC10 => {
+        AF0: TxPin<USART4>,
+        AF1: TxPin<USART3>
+    },
+    PC11 => {
+        AF0: RxPin<USART4>,
+        AF1: RxPin<USART3>
+    },
+    PC0 => {AF2: TxPin<USART6>},
+    PC1 => {AF2: RxPin<USART6>},
+    PC12 => {AF2: RxPin<USART5>},
+    PD2 => {AF2: TxPin<USART5>}
+}
+
+#[cfg(feature = "stm32f030x6")]
+pins! {
+    PA2 => {AF1: TxPin<USART1>},
+    PA3 => {AF1: RxPin<USART1>},
+    PA9 => {AF4: SclPin<I2C1>},
+    PA10 => {AF4: SdaPin<I2C1>},
+    PA14 => {AF1: TxPin<USART1>},
+    PA15 => {AF1: RxPin<USART1>},
+    PB10 => {AF1: SclPin<I2C1>},
+    PB11 => {AF1: SdaPin<I2C1>},
+    PB13 => {AF0: SckPin<SPI1>},
+    PB14 => {AF0: MisoPin<SPI1>},
+    PB15 => {AF0: MosiPin<SPI1>}
+}
+
+#[cfg(any(feature = "stm32f030x8", feature = "stm32f030xc"))]
+pins! {
+    PA2 => {AF1: TxPin<USART2>},
+    PA3 => {AF1: RxPin<USART2>},
+    PA14 => {AF1: TxPin<USART2>},
+    PA15 => {AF1: RxPin<USART2>},
+    PB10 => {AF1: SclPin<I2C2>},
+    PB11 => {AF1: SdaPin<I2C1>},
+    PB13 => {AF0: SckPin<SPI2>},
+    PB14 => {AF0: MisoPin<SPI2>},
+    PB15 => {AF0: MosiPin<SPI2>}
+}
+
+#[cfg(any(feature = "stm32f030xc",))]
+pins! {
+    PA9 => {AF4: SclPin<I2C1>},
+    PA10 => {AF4: SdaPin<I2C1>},
+    PB13 => {AF5: SclPin<I2C1>},
+    PB14 => {AF5: SdaPin<I2C1>},
+    PF0 => {AF1: SdaPin<I2C1>},
+    PF1 => {AF1: SclPin<I2C1>}
+}
+
+#[cfg(feature = "stm32f042")]
+pins! {
+    PA11 => {AF5: SclPin<I2C1>},
+    PA12 => {AF5: SdaPin<I2C1>},
+    PA2 => {AF1: TxPin<USART2>},
+    PA3 => {AF1: RxPin<USART2>},
+    PA9 => {AF4: SclPin<I2C1>},
+    PA10 => {AF4: SdaPin<I2C1>},
+    PA14 => {AF1: TxPin<USART2>},
+    PA15 => {AF1: RxPin<USART2>},
+    PB10 => {AF1: SclPin<I2C1>},
+    PB11 => {AF1: SdaPin<I2C1>},
+    PB13 => {AF5: SclPin<I2C1>},
+    PB14 => {AF5: SdaPin<I2C1>},
+    PF0 => {AF1: SdaPin<I2C1>},
+    PF1 => {AF1: SclPin<I2C1>}
+}
+
+#[cfg(feature = "stm32f070")]
+pins! {
+    PA0 => {AF4: TxPin<USART4>},
+    PA1 => {AF4: RxPin<USART4>},
+    PA2 => {AF1: TxPin<USART2>},
+    PA3 => {AF1: RxPin<USART2>},
+    PA14 => {AF1: TxPin<USART2>},
+    PA15 => {AF1: RxPin<USART2>},
+    PB10 => {
+        AF4: TxPin<USART3>,
+        AF5: SckPin<SPI2>
+    },
+    PB11 => {AF4: RxPin<USART3>},
+    PC2 => {AF1: MisoPin<SPI2>},
+    PC3 => {AF1: MosiPin<SPI2>},
+    PC4 => {AF1: TxPin<USART3>},
+    PC5 => {AF1: RxPin<USART3>},
+    PC10 => {
+        AF0: TxPin<USART4>,
+        AF1: TxPin<USART3>
+    },
+    PC11 => {
+        AF0: RxPin<USART4>,
+        AF1: RxPin<USART3>
+    }
+}
+
+#[cfg(feature = "stm32f070xb")]
+pins! {
+    PB10 => {AF1: SclPin<I2C1>},
+    PB11 => {AF1: SdaPin<I2C1>},
+    PB13 => {AF0: SckPin<SPI2>},
+    PB14 => {AF0: MisoPin<SPI2>},
+    PB13 => {AF5: SclPin<I2C1>},
+    PB14 => {AF5: SdaPin<I2C1>},
+    PB15 => {AF0: MosiPin<SPI2>}
+}
+#[cfg(feature = "stm32f070x6")]
+pins! {
+    PA9 => {AF4: SclPin<I2C1>},
+    PA10 => {AF4: SdaPin<I2C1>},
+    PF0 => {AF1: SdaPin<I2C1>},
+    PF1 => {AF1: SclPin<I2C1>}
+}
diff --git a/src/serial.rs b/src/serial.rs
index 504bf6a..701870a 100644
--- a/src/serial.rs
+++ b/src/serial.rs
@@ -98,165 +98,6 @@ pub enum Event {
 pub trait TxPin<USART> {}
 pub trait RxPin<USART> {}
 
-macro_rules! usart_pins {
-    ($($USART:ident => {
-        tx => [$($tx:ty),+ $(,)*],
-        rx => [$($rx:ty),+ $(,)*],
-    })+) => {
-        $(
-            $(
-                impl TxPin<crate::stm32::$USART> for $tx {}
-            )+
-            $(
-                impl RxPin<crate::stm32::$USART> for $rx {}
-            )+
-        )+
-    }
-}
-
-#[cfg(any(
-    feature = "stm32f030",
-    feature = "stm32f031",
-    feature = "stm32f038",
-    feature = "stm32f042",
-    feature = "stm32f048",
-    feature = "stm32f051",
-    feature = "stm32f058",
-    feature = "stm32f070",
-    feature = "stm32f071",
-    feature = "stm32f072",
-    feature = "stm32f078",
-    feature = "stm32f091",
-    feature = "stm32f098",
-))]
-usart_pins! {
-    USART1 => {
-        tx => [gpioa::PA9<Alternate<AF1>>, gpiob::PB6<Alternate<AF0>>],
-        rx => [gpioa::PA10<Alternate<AF1>>, gpiob::PB7<Alternate<AF0>>],
-    }
-}
-#[cfg(any(
-    feature = "stm32f030x4",
-    feature = "stm32f030x6",
-    feature = "stm32f031",
-    feature = "stm32f038",
-))]
-usart_pins! {
-    USART1 => {
-        tx => [gpioa::PA2<Alternate<AF1>>, gpioa::PA14<Alternate<AF1>>],
-        rx => [gpioa::PA3<Alternate<AF1>>, gpioa::PA15<Alternate<AF1>>],
-    }
-}
-
-#[cfg(any(
-    feature = "stm32f030x8",
-    feature = "stm32f030xc",
-    feature = "stm32f042",
-    feature = "stm32f048",
-    feature = "stm32f051",
-    feature = "stm32f058",
-    feature = "stm32f070",
-    feature = "stm32f071",
-    feature = "stm32f072",
-    feature = "stm32f078",
-    feature = "stm32f091",
-    feature = "stm32f098",
-))]
-usart_pins! {
-    USART2 => {
-        tx => [gpioa::PA2<Alternate<AF1>>, gpioa::PA14<Alternate<AF1>>],
-        rx => [gpioa::PA3<Alternate<AF1>>, gpioa::PA15<Alternate<AF1>>],
-    }
-}
-#[cfg(any(
-    feature = "stm32f071",
-    feature = "stm32f072",
-    feature = "stm32f078",
-    feature = "stm32f091",
-    feature = "stm32f098",
-))]
-usart_pins! {
-    USART2 => {
-        tx => [gpiod::PD5<Alternate<AF0>>],
-        rx => [gpiod::PD6<Alternate<AF0>>],
-    }
-}
-
-#[cfg(any(
-    feature = "stm32f030xc",
-    feature = "stm32f070xb",
-    feature = "stm32f071",
-    feature = "stm32f072",
-    feature = "stm32f078",
-    feature = "stm32f091",
-    feature = "stm32f098",
-))]
-usart_pins! {
-    USART3 => {
-        // According to the datasheet PB10 is both tx and rx, but in stm32cubemx it's only tx
-        tx => [gpiob::PB10<Alternate<AF4>>, gpioc::PC4<Alternate<AF1>>, gpioc::PC10<Alternate<AF1>>],
-        rx => [gpiob::PB11<Alternate<AF4>>, gpioc::PC5<Alternate<AF1>>, gpioc::PC11<Alternate<AF1>>],
-    }
-    USART4 => {
-        tx => [gpioa::PA0<Alternate<AF4>>, gpioc::PC10<Alternate<AF0>>],
-        rx => [gpioa::PA1<Alternate<AF4>>, gpioc::PC11<Alternate<AF0>>],
-    }
-}
-#[cfg(any(
-    feature = "stm32f071",
-    feature = "stm32f072",
-    feature = "stm32f078",
-    feature = "stm32f091",
-    feature = "stm32f098",
-))]
-usart_pins! {
-    USART3 => {
-        tx => [gpiod::PD8<Alternate<AF0>>],
-        rx => [gpiod::PD9<Alternate<AF0>>],
-    }
-}
-// TODO: The ST SVD files are missing the entire PE enable register.
-//       Re-enable as soon as this gets fixed.
-// #[cfg(any(feature = "stm32f091", feature = "stm32f098"))]
-// usart_pins! {
-//     USART4 => {
-//         tx => [gpioe::PE8<Alternate<AF1>>],
-//         rx => [gpioe::PE9<Alternate<AF1>>],
-//     }
-// }
-
-#[cfg(any(feature = "stm32f030xc", feature = "stm32f091", feature = "stm32f098"))]
-usart_pins! {
-    USART5 => {
-        tx => [gpioc::PC12<Alternate<AF2>>],
-        rx => [gpiod::PD2<Alternate<AF2>>],
-    }
-    USART6 => {
-        tx => [gpioa::PA4<Alternate<AF5>>, gpioc::PC0<Alternate<AF2>>],
-        rx => [gpioa::PA5<Alternate<AF5>>, gpioc::PC1<Alternate<AF2>>],
-    }
-}
-#[cfg(any(feature = "stm32f030xc", feature = "stm32f091"))]
-usart_pins! {
-    USART5 => {
-        tx => [gpiob::PB3<Alternate<AF4>>],
-        rx => [gpiob::PB4<Alternate<AF4>>],
-    }
-}
-// TODO: The ST SVD files are missing the entire PE enable register.
-//       Re-enable as soon as this gets fixed.
-#[cfg(any(feature = "stm32f091", feature = "stm32f098"))]
-usart_pins! {
-    // USART5 => {
-    //     tx => [gpioe::PE10<Alternate<AF1>>],
-    //     rx => [gpioe::PE11<Alternate<AF1>>],
-    // }
-    USART6 => {
-        tx => [gpiof::PF9<Alternate<AF1>>],
-        rx => [gpiof::PF10<Alternate<AF1>>],
-    }
-}
-
 /// Serial abstraction
 pub struct Serial<USART, TXPIN, RXPIN> {
     usart: USART,
diff --git a/src/spi.rs b/src/spi.rs
index 7ed5c1b..96b0963 100644
--- a/src/spi.rs
+++ b/src/spi.rs
@@ -91,116 +91,6 @@ pub trait SckPin<SPI> {}
 pub trait MisoPin<SPI> {}
 pub trait MosiPin<SPI> {}
 
-macro_rules! spi_pins {
-    ($($SPI:ident => {
-        sck => [$($sck:ty),+ $(,)*],
-        miso => [$($miso:ty),+ $(,)*],
-        mosi => [$($mosi:ty),+ $(,)*],
-    })+) => {
-        $(
-            $(
-                impl SckPin<crate::stm32::$SPI> for $sck {}
-            )+
-            $(
-                impl MisoPin<crate::stm32::$SPI> for $miso {}
-            )+
-            $(
-                impl MosiPin<crate::stm32::$SPI> for $mosi {}
-            )+
-        )+
-    }
-}
-
-spi_pins! {
-    SPI1 => {
-        sck => [gpioa::PA5<Alternate<AF0>>, gpiob::PB3<Alternate<AF0>>],
-        miso => [gpioa::PA6<Alternate<AF0>>, gpiob::PB4<Alternate<AF0>>],
-        mosi => [gpioa::PA7<Alternate<AF0>>, gpiob::PB5<Alternate<AF0>>],
-    }
-}
-#[cfg(any(
-    feature = "stm32f030x4",
-    feature = "stm32f030x6",
-    feature = "stm32f031",
-    feature = "stm32f038",
-))]
-spi_pins! {
-    SPI1 => {
-        sck => [gpiob::PB13<Alternate<AF0>>],
-        miso => [gpiob::PB14<Alternate<AF0>>],
-        mosi => [gpiob::PB15<Alternate<AF0>>],
-    }
-}
-// TODO: The ST SVD files are missing the entire PE enable register.
-//       So those pins do not exist in the register definitions.
-//       Re-enable as soon as this gets fixed.
-// #[cfg(any(
-//     feature = "stm32f071",
-//     feature = "stm32f072",
-//     feature = "stm32f078",
-//     feature = "stm32f091",
-//     feature = "stm32f098",
-// ))]
-// spi_pins! {
-//     SPI1 => {
-//         sck => [gpioe::PE13<Alternate<AF1>>],
-//         miso => [gpioe::PE14<Alternate<AF1>>],
-//         mosi => [gpioe::PE15<Alternate<AF1>>],
-//     }
-// }
-
-#[cfg(any(
-    feature = "stm32f030x8",
-    feature = "stm32f030xc",
-    feature = "stm32f042",
-    feature = "stm32f048",
-    feature = "stm32f051",
-    feature = "stm32f058",
-    feature = "stm32f070xb",
-    feature = "stm32f071",
-    feature = "stm32f072",
-    feature = "stm32f078",
-    feature = "stm32f091",
-    feature = "stm32f098",
-))]
-spi_pins! {
-    SPI2 => {
-        sck => [gpiob::PB13<Alternate<AF0>>],
-        miso => [gpiob::PB14<Alternate<AF0>>],
-        mosi => [gpiob::PB15<Alternate<AF0>>],
-    }
-}
-#[cfg(any(
-    feature = "stm32f030xc",
-    feature = "stm32f070xb",
-    feature = "stm32f071",
-    feature = "stm32f072",
-    feature = "stm32f078",
-    feature = "stm32f091",
-    feature = "stm32f098",
-))]
-spi_pins! {
-    SPI2 => {
-        sck => [gpiob::PB10<Alternate<AF5>>],
-        miso => [gpioc::PC2<Alternate<AF1>>],
-        mosi => [gpioc::PC3<Alternate<AF1>>],
-    }
-}
-#[cfg(any(
-    feature = "stm32f071",
-    feature = "stm32f072",
-    feature = "stm32f078",
-    feature = "stm32f091",
-    feature = "stm32f098",
-))]
-spi_pins! {
-    SPI2 => {
-        sck => [gpiod::PD1<Alternate<AF1>>],
-        miso => [gpiod::PD3<Alternate<AF1>>],
-        mosi => [gpiod::PD4<Alternate<AF1>>],
-    }
-}
-
 macro_rules! spi {
     ($($SPI:ident: ($spi:ident, $spiXen:ident, $spiXrst:ident, $apbenr:ident, $apbrstr:ident),)+) => {
         $(