remove interrupt state caching that is not required by RM, don't include L4P/L4Q anywhere yet

Author: Crzyrndm

src/lib.rs

@@ -64,12 +64,14 @@ pub use stm32l4;
 #[cfg(feature = "private_line_stm32l4x1")]
 pub use stm32l4::stm32l4x1 as pac;
 
-#[cfg(any(feature = "stm32l412", feature = "stm32l422"))]
+#[cfg(all(
+    feature = "private_product_L41_L42",
+    feature = "private_line_stm32l4x2"
+))]
 pub use stm32l4::stm32l412 as pac; // L412 doesn't use the generic L4x2 PAC defines
 #[cfg(all(
     feature = "private_line_stm32l4x2",
-    not(feature = "stm32l412"),
-    not(feature = "stm32l422")
+    not(feature = "private_product_L41_L42"),
 ))]
 pub use stm32l4::stm32l4x2 as pac; // Generic L4x2 PAC
 

src/rtc.rs

@@ -219,20 +219,18 @@ impl Rtc {
         // HAL_RTC_SetAlarm_IT[L1921-L2098]
         self.write(false, |rtc| match alarm {
             Alarm::AlarmA => {
-                let interrupt_enabled = rtc.cr.read().alraie().bit(); // cache interrupt state
-                rtc.cr
-                    .modify(|_, w| w.alrae().clear_bit().alraie().clear_bit()); // Disable the Alarm A interrupt
+                rtc.cr.modify(|_, w| w.alrae().clear_bit()); // Disable the Alarm A interrupt
                 #[cfg(any(
                     feature = "private_product_L41_L42",
-                    feature = "private_product_L4P_L4Q"
+                    //feature = "private_product_L4P_L4Q"
                 ))]
                 {
                     rtc.scr.write(|w| w.calraf().set_bit());
                     // no waiting
                 }
                 #[cfg(not(any(
                     feature = "private_product_L41_L42",
-                    feature = "private_product_L4P_L4Q"
+                    //feature = "private_product_L4P_L4Q"
                 )))]
                 {
                     rtc.isr.modify(|_, w| w.alraf().clear_bit());
@@ -268,25 +266,22 @@ impl Rtc {
                 // write the SS value and mask to `rtc.alrmassr`
 
                 // enable alarm and reenable interrupt if it was enabled
-                rtc.cr
-                    .modify(|_, w| w.alrae().set_bit().alraie().bit(interrupt_enabled));
+                rtc.cr.modify(|_, w| w.alrae().set_bit());
             }
             Alarm::AlarmB => {
-                let interrupt_enabled = rtc.cr.read().alrbie().bit(); // cache interrupt state
-                rtc.cr
-                    .modify(|_, w| w.alrbe().clear_bit().alraie().clear_bit());
+                rtc.cr.modify(|_, w| w.alrbe().clear_bit());
 
                 #[cfg(any(
                     feature = "private_product_L41_L42",
-                    feature = "private_product_L4P_L4Q"
+                    // feature = "private_product_L4P_L4Q"
                 ))]
                 {
                     rtc.scr.write(|w| w.calrbf().set_bit());
                     // no waiting
                 }
                 #[cfg(not(any(
                     feature = "private_product_L41_L42",
-                    feature = "private_product_L4P_L4Q"
+                    // feature = "private_product_L4P_L4Q"
                 )))]
                 {
                     rtc.isr.modify(|_, w| w.alrbf().clear_bit());
@@ -322,8 +317,7 @@ impl Rtc {
                 // write the SS value and mask to `rtc.alrmassr`
 
                 // enable alarm and reenable interrupt if it was enabled
-                rtc.cr
-                    .modify(|_, w| w.alrbe().set_bit().alrbie().bit(interrupt_enabled));
+                rtc.cr.modify(|_, w| w.alrbe().set_bit());
             }
         });
     }