Initial import

Author: jserv

.gitignore

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+emu-rv32i
+test1

AUTHORS

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+Fabrice Bellard - original code of RISC-V emulator:
+https://bellard.org/tinyemu/
+
+Frank Buss - simplified emulator for RV32I capable of passing compliance tests:
+https://gist.github.com/FrankBuss/c974e59826d33e21d7cad54491ab50e8
+
+Alexander Shabarshin - maintainer of this nedoPC-5 project:
+https://gitlab.com/nedopc/npc5

LICENSE

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+Original MIT License:
+
+Copyright (c) 2016-2017 Fabrice Bellard
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.

Makefile

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+BINS = emu-rv32i test1
+
+CROSS_COMPILE = riscv-none-embed-
+RV32I_CFLAGS = -march=rv32i -mabi=ilp32 -O3 -nostdlib
+
+CFLAGS = -O3 -Wall
+LDFLAGS = -lelf
+
+all: $(BINS)
+	
+emu-rv32i: emu-rv32i.c
+	$(CC) $(CFLAGS) -o $@ $< $(LDFLAGS)
+
+test1: test1.c
+	$(CROSS_COMPILE)gcc $(RV32I_CFLAGS) -o $@ $<
+
+check: $(BINS)
+	./emu-rv32i test1
+
+clean:
+	$(RM) $(BINS)

README.md

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+# RISC-V RV32I[MA] emulator with ELF support
+
+Emulator was originally created by Fabrice Bellard and then modified and shared on Hackaday by Frank Buss
+as a single C-file. Shaos added some additional statistics and macros. How to compile it:
+
+    gcc -O3 -Wall -lelf emu-rv32i.c -o emu-rv32i
+
+Passed RV32I compliance tests from https://github.com/riscv/riscv-compliance
+
+    make RISCV_TARGET=spike RISCV_DEVICE=rv32i TARGET_SIM=/full/path/emulator variant
+
+Compiling and running simple code:
+
+    riscv32-unknown-elf-gcc -O3 -nostdlib test1.c -o test1
+
+or
+
+    riscv64-unknown-elf-gcc -march=rv32i -mabi=ilp32 -O3 -nostdlib test1.c -o test1
+
+then
+
+    ./emu-rv32i test1
+    Hello RISC-V!
+
+RV32M and RV32A instructions may be enabled by commenting #define STRICT_RV32I
+
+## How to build RISC-V toolchain from scratch
+
+https://github.com/riscv/riscv-gnu-toolchain
+
+64-bit universal version (riscv64-unknown-elf-* that can build 32-bit code too):
+
+    ./configure --prefix=/opt/riscv
+    make
+
+32-bit version (riscv32-unknown-elf-*):
+
+    ./configure --prefix=/opt/riscv32 --with-arch=rv32i --with-abi=ilp32
+    make