Drop useless CVS stuff in .txt files

Remove useless, redundant, misleading, and misspelled $Id$ and $Log$
cruft from all .txt files.

Author: ldoolitt

cadpli/cadpli.txt

@@ -2,7 +2,6 @@
 CADENCE PLI1 MODULES
 
    Copyright 2003 Stephen Williams
-   $Id: cadpli.txt,v 1.2 2003/02/17 00:01:25 steve Exp $
 
 With the cadpli module, Icarus Verilog is able to load PLI1
 applications that were compiled and linked to be dynamic loaded by
@@ -34,15 +33,3 @@ the +loadpli1= argument to Verilog-XL.
 The integration from this point is seamless. The PLI application
 hardly knows that it is being invoked by Icarus Verilog instead of
 Verilog-XL, so operates as it would otherwise.
-
-$Log: cadpli.txt,v $
-Revision 1.2  2003/02/17 00:01:25  steve
- Use a variant of ivl_dlfcn to do dynamic loading
- from within the cadpli module.
-
- Change the +cadpli flag to -cadpli, to keep the
- plusargs namespace clear.
-
-Revision 1.1  2003/02/16 02:44:47  steve
- Add the cadpli HOWTO.
-

ieee1364-notes.txt

@@ -499,65 +499,3 @@ already seems to exist amongst VCD viewers in the wild, this behavior
 seems to be acceptable according to the standard, is a better mirror
 of 4-value behavior in the dead zone, and appears more user friendly
 when viewed by reasonable viewers.
-
-
-$Id: ieee1364-notes.txt,v 1.19 2007/04/18 02:36:13 steve Exp $
-$Log: ieee1364-notes.txt,v $
-Revision 1.19  2007/04/18 02:36:13  steve
- Put to iverilog wiki for further notes.
-
-Revision 1.18  2007/03/22 16:08:16  steve
- Spelling fixes from Larry
-
-Revision 1.17  2003/07/15 03:49:22  steve
- Spelling fixes.
-
-Revision 1.16  2003/04/14 03:40:21  steve
- Make some effort to preserve bits while
- operating on constant values.
-
-Revision 1.15  2003/02/16 23:39:08  steve
- NaN in dead zones of VCD dumps.
-
-Revision 1.14  2003/02/06 17:51:36  steve
- Edge of vectors notes.
-
-Revision 1.13  2002/08/20 04:11:53  steve
- Support parameters with defined ranges.
-
-Revision 1.12  2002/06/11 03:34:33  steve
- Spelling patch (Larry Doolittle)
-
-Revision 1.11  2002/04/27 02:38:04  steve
- Support selecting bits from parameters.
-
-Revision 1.10  2002/03/31 01:54:13  steve
- Notes about scheduling
-
-Revision 1.9  2002/01/26 02:08:07  steve
- Handle x in l-value of set/x
-
-Revision 1.8  2001/08/01 05:17:31  steve
- Accept empty port lists to module instantiation.
-
-Revision 1.7  2001/02/17 05:27:31  steve
- I allow function ports to have types.
-
-Revision 1.6  2001/02/12 16:48:04  steve
- Rant about bit widths.
-
-Revision 1.5  2001/01/02 17:28:08  steve
- Resolve repeat ambiguity in favor of loop.
-
-Revision 1.4  2001/01/01 19:12:35  steve
- repeat loops ambiguity.
-
-Revision 1.3  2000/12/15 00:21:46  steve
- rounding of time and x in primitives.
-
-Revision 1.2  2000/11/19 22:03:04  steve
- Integer parameter comments.
-
-Revision 1.1  2000/07/23 18:06:31  steve
- Document ieee1364 issues.
-

ivl_target.txt

@@ -2,7 +2,6 @@
 Icarus Verilog LOADABLE TARGET API (ivl_target)
 
   Copyright 2002 Stephen Williams <[email protected]>
-  $Id: ivl_target.txt,v 1.3 2002/06/11 03:34:33 steve Exp $
 
 
 The ivl_target API is the interface available to modules that the
@@ -38,14 +37,3 @@ other LPM device with outputs.
 
 There are ivl_lpm_size() input ports, each with the width
 ivl_lpm_data2_width(). The actual nexus is indexed by ivl_lpm_data2().
-
-$Log: ivl_target.txt,v $
-Revision 1.3  2002/06/11 03:34:33  steve
- Spelling patch (Larry Doolittle)
-
-Revision 1.2  2002/03/17 19:31:17  steve
- Add API to support user defined function.
-
-Revision 1.1  2002/03/09 02:10:22  steve
- Add the NetUserFunc netlist node.
-

netlist.txt

@@ -16,7 +16,6 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#ident "$Id: netlist.txt,v 1.10 2000/07/23 18:06:15 steve Exp $"
 
 
 Note that the netlist.h header contains detailed descriptions of how
@@ -291,49 +290,3 @@ values. These are filled in during scope elaboration and are used in
 subsequent elaboration phases to arrange for scaling of delays. This
 information can also be used by the code generator to scale times back
 to the units of the scope, if that is desired.
-
- $Log: netlist.txt,v $
- Revision 1.10  2000/07/23 18:06:15  steve
-  Document time scale in netlists.
-
- Revision 1.9  2000/07/14 06:12:57  steve
-  Move inital value handling from NetNet to Nexus
-  objects. This allows better propogation of inital
-  values.
-
-  Clean up constant propagation  a bit to account
-  for regs that are not really values.
-
- Revision 1.8  2000/03/08 04:36:54  steve
-  Redesign the implementation of scopes and parameters.
-  I now generate the scopes and notice the parameters
-  in a separate pass over the pform. Once the scopes
-  are generated, I can process overrides and evalutate
-  paremeters before elaboration begins.
-
- Revision 1.7  1999/11/28 23:42:02  steve
-  NetESignal object no longer need to be NetNode
-  objects. Let them keep a pointer to NetNet objects.
-
- Revision 1.6  1999/11/21 00:13:09  steve
-  Support memories in continuous assignments.
-
- Revision 1.5  1999/11/02 04:55:34  steve
-  Add the synthesize method to NetExpr to handle
-  synthesis of expressions, and use that method
-  to improve r-value handling of LPM_FF synthesis.
-
-  Modify the XNF target to handle LPM_FF objects.
-
- Revision 1.4  1999/09/29 00:03:27  steve
-  Spelling fixes from Larry.
-
- Revision 1.3  1999/07/24 02:11:20  steve
-  Elaborate task input ports.
-
- Revision 1.2  1999/07/21 01:15:29  steve
-  Document netlist semantics.
-
- Revision 1.1  1999/05/27 04:13:08  steve
-  Handle expression bit widths with non-fatal errors.
-

solaris/README-solaris_pkg.txt

@@ -1,5 +1,3 @@
-# $Id: README-solaris_pkg.txt,v 1.3 2007/02/26 19:49:49 steve Exp $
-
 Notes about the solaris package.
 
 I.  Installing a prebuilt solaris package

tgt-fpga/fpga.txt

@@ -2,7 +2,6 @@
 FPGA LOADABLE CODE GENERATOR FOR Icarus Verilog
 
   Copyright 2001 Stephen Williams
-  $Id: fpga.txt,v 1.12 2005/09/19 21:45:36 steve Exp $
 
 The FPGA code generator supports a variety of FPGA devices, writing
 XNF or EDIF depending on the target. You can select the architecture
@@ -186,42 +185,3 @@ Compile a single-file design with command line tools like so:
 	% map -o map.ncd foo.ngd
 	% par -w map.ncd foo.ncd
 
----
-$Log: fpga.txt,v $
-Revision 1.12  2005/09/19 21:45:36  steve
- Spelling patches from Larry.
-
-Revision 1.11  2003/08/07 05:17:34  steve
- Add arch=lpm to the documentation.
-
-Revision 1.10  2003/07/04 03:57:19  steve
- Allow attributes on Verilog 2001 port declarations.
-
-Revision 1.9  2003/07/04 01:08:03  steve
- PAD attribute can be used to assign pins.
-
-Revision 1.8  2003/07/02 00:26:49  steve
- Fix spelling of part= flag.
-
-Revision 1.7  2003/03/24 02:28:38  steve
- Document the virtex2 architecture.
-
-Revision 1.6  2003/03/24 00:47:54  steve
- Add new virtex2 architecture family, and
- also the new edif.h EDIF management functions.
-
-Revision 1.5  2002/04/30 04:26:42  steve
- Spelling errors.
-
-Revision 1.4  2001/09/16 22:26:47  steve
- Support the cellref attribute.
-
-Revision 1.3  2001/09/16 01:48:16  steve
- Suppor the PAD attribute on signals.
-
-Revision 1.2  2001/09/06 04:28:40  steve
- Separate the virtex and generic-edif code generators.
-
-Revision 1.1  2001/09/02 23:58:49  steve
- Add documentation for the code generator.
-

vvp/README.txt

@@ -1,7 +1,6 @@
 /*
  * Copyright (c) 2001 Stephen Williams ([email protected])
  *
- *  $Id: README.txt,v 1.82 2007/03/22 16:08:19 steve Exp $
  */
 
 VVP SIMULATION ENGINE

vvp/vpi.txt

@@ -1,7 +1,6 @@
 /*
  * Copyright (c) 2001 Stephen Williams ([email protected])
  *
- *  $Id: vpi.txt,v 1.8 2007/03/22 16:08:19 steve Exp $
  */
 
 

vvp/vthread.txt

@@ -1,7 +1,6 @@
 /*
  * Copyright (c) 2001 Stephen Williams ([email protected])
  *
- *  $Id: vthread.txt,v 1.6 2005/09/19 21:45:37 steve Exp $
  */