Handle some tricky conditions assignments to parts.

When for example assigning to foo[<x>] within a contitional, and
doing synthesis, we need to create a NetSubstitute device to manage
the l-value bit selects.

Author: steveicarus

design_dump.cc

@@ -778,6 +778,21 @@ void NetPartSelect::dump_node(ostream&o, unsigned ind) const
       dump_obj_attr(o, ind+4);
 }
 
+void NetSubstitute::dump_node(ostream&fd, unsigned ind) const
+{
+      fd << setw(ind) << "" << "NetSubstitute: "
+	 << name();
+      if (rise_time())
+	    fd << " #(" << *rise_time()
+	       << "," << *fall_time()
+	       << "," << *decay_time() << ")";
+      else
+	    fd << " #(.,.,.)";
+      fd << " width=" << wid_ << " base=" << off_ <<endl;
+      dump_node_pins(fd, ind+4);
+      dump_obj_attr(fd, ind+4);
+}
+
 void NetReplicate::dump_node(ostream&o, unsigned ind) const
 {
       o << setw(ind) << "" << "NetReplicate: "

emit.cc

@@ -167,6 +167,11 @@ bool NetSignExtend::emit_node(struct target_t*tgt) const
       return tgt->sign_extend(this);
 }
 
+bool NetSubstitute::emit_node(struct target_t*tgt) const
+{
+      return tgt->substitute(this);
+}
+
 bool NetUReduce::emit_node(struct target_t*tgt) const
 {
       return tgt->ureduce(this);

ivl_target.h

@@ -328,6 +328,7 @@ typedef enum ivl_lpm_type_e {
       IVL_LPM_SHIFTR =  7,
       IVL_LPM_SIGN_EXT=27,
       IVL_LPM_SUB    =  8,
+      IVL_LPM_SUBSTITUTE=39,
       /* IVL_LPM_RAM =  9, / obsolete */
       IVL_LPM_UFUNC  = 14
 } ivl_lpm_type_t;
@@ -1409,7 +1410,7 @@ extern ivl_nexus_t ivl_lpm_sync_set(ivl_lpm_t net);
 extern ivl_expr_t  ivl_lpm_sset_value(ivl_lpm_t net);
   /* IVL_LPM_ARRAY */
 extern ivl_signal_t ivl_lpm_array(ivl_lpm_t net);
-  /* IVL_LPM_PART */
+  /* IVL_LPM_PART IVL_LPM_SUBSTITUTE */
 extern unsigned ivl_lpm_base(ivl_lpm_t net);
   /* IVL_LPM_FF */
 extern ivl_nexus_t ivl_lpm_clk(ivl_lpm_t net);
@@ -1419,14 +1420,14 @@ extern ivl_scope_t  ivl_lpm_define(ivl_lpm_t net);
 extern ivl_nexus_t ivl_lpm_enable(ivl_lpm_t net);
   /* IVL_LPM_ADD IVL_LPM_CONCAT IVL_LPM_FF IVL_LPM_PART IVL_LPM_MULT
      IVL_LPM_MUX IVL_LPM_POW IVL_LPM_SHIFTL IVL_LPM_SHIFTR IVL_LPM_SUB
-     IVL_LPM_UFUNC */
+     IVL_LPM_UFUNC IVL_LPM_SUBSTITUTE */
 extern ivl_nexus_t ivl_lpm_data(ivl_lpm_t net, unsigned idx);
   /* IVL_LPM_ADD IVL_LPM_MULT IVL_LPM_POW IVL_LPM_SUB IVL_LPM_CMP_EQ
      IVL_LPM_CMP_EEQ IVL_LPM_CMP_EQX IVL_LPM_CMP_EQZ IVL_LPM_CMP_NEE */
 extern ivl_nexus_t ivl_lpm_datab(ivl_lpm_t net, unsigned idx);
   /* IVL_LPM_ADD IVL_LPM_FF IVL_LPM_MULT IVL_LPM_PART IVL_LPM_POW
      IVL_LPM_SUB IVL_LPM_UFUNC IVL_LPM_CMP_EEQ IVL_LPM_CMP_EQX
-     IVL_LPM_CMP_EQZ IVL_LPM_CMP_NEE */
+     IVL_LPM_CMP_EQZ IVL_LPM_CMP_NEE IVL_LPM_SUBSTITUTE */
 extern ivl_nexus_t ivl_lpm_q(ivl_lpm_t net);
 extern ivl_drive_t ivl_lpm_drive0(ivl_lpm_t net);
 extern ivl_drive_t ivl_lpm_drive1(ivl_lpm_t net);

net_nex_output.cc

@@ -60,19 +60,18 @@ void NetAssign_::nex_output(NexusSet&out)
       }
       Nexus*nex = sig_->pin(use_word).nexus();
       if (base_) {
-	    long tmp = 0;
-	    bool flag = eval_as_long(tmp, base_);
-	    if (!flag) {
-		    // Unable to evaluate the bit/part select of
-		    // the l-value, so this is a mux. Pretty
-		    // sure I don't know how to handle this yet
-		    // in synthesis, so punt for now.
-		  use_base = 0;
-		  use_wid = nex->vector_width();
 
-	    } else {
-		  use_base = tmp;
-	    }
+	      // Unable to evaluate the bit/part select of
+	      // the l-value, so this is a mux. Pretty
+	      // sure I don't know how to handle this yet
+	      // in synthesis, so punt for now.
+
+	      // Even with constant bit/part select, we want to
+	      // return the entire signal as an output. The
+	      // context will need to sort out which bits are
+	      // actually assigned.
+	    use_base = 0;
+	    use_wid = nex->vector_width();
       }
       out.add(nex, use_base, use_wid);
 }

netlist.cc

@@ -989,6 +989,20 @@ unsigned NetPartSelect::base() const
       return off_;
 }
 
+NetSubstitute::NetSubstitute(NetNet*sig, NetNet*sub, unsigned wid, unsigned off)
+: NetNode(sig->scope(), sig->scope()->local_symbol(), 3), wid_(wid), off_(off)
+{
+      pin(0).set_dir(Link::OUTPUT);
+      pin(1).set_dir(Link::INPUT);
+      pin(2).set_dir(Link::INPUT);
+      connect(pin(1), sig->pin(0));
+      connect(pin(2), sub->pin(0));
+}
+
+NetSubstitute::~NetSubstitute()
+{
+}
+
 NetProc::NetProc()
 : next_(0)
 {

netlist.h

@@ -2192,6 +2192,40 @@ class NetPartSelect  : public NetNode {
       bool signed_flag_;
 };
 
+/*
+ * This device supports simple substitution of a part within a wider
+ * vector. For example, this:
+ *
+ *      wire [7:0] foo = NetSubstitute(bar, bat, off);
+ *
+ * meaus that bar is a vector the same width as foo, bat is a narrower
+ * vector. The off is a constant offset into the bar vector. This
+ * looks something like this:
+ *
+ *      foo = bar;
+ *      foo[off +: <width_of_bat>] = bat;
+ *
+ * There is no direct way in Verilog to express this (as a single
+ * device), it instead turns up in certain synthesis situation,
+ * i.e. the example above.
+ */
+class NetSubstitute : public NetNode {
+
+    public:
+      NetSubstitute(NetNet*sig, NetNet*sub, unsigned wid, unsigned off);
+      ~NetSubstitute();
+
+      inline unsigned width() const { return wid_; }
+      inline unsigned base() const  { return off_; }
+
+      virtual void dump_node(ostream&, unsigned ind) const;
+      virtual bool emit_node(struct target_t*tgt) const;
+
+    private:
+      unsigned wid_;
+      unsigned off_;
+};
+
 /*
  * The NetBUFZ is a magic device that represents the continuous
  * assign, with the output being the target register and the input