Fixed warnings about shifting a negative value

Author: msuminsk

tgt-vhdl/stmt.cc

@@ -1180,7 +1180,7 @@ static long get_number_as_long(ivl_expr_t expr)
          }
 
          if (ivl_expr_signed(expr) && bits[nbits-1] == '1' &&
-             nbits < 8*sizeof(long)) imm |= -1L << nbits;
+             nbits < 8*sizeof(long)) imm |= -1UL << nbits;
       }
       break;
    }

tgt-vvp/eval_expr.c

@@ -139,7 +139,7 @@ long get_number_immediate(ivl_expr_t expr)
 		      assert(0);
 		}
 		if (ivl_expr_signed(expr) && bits[nbits-1]=='1' &&
-		    nbits < 8*sizeof(long)) imm |= -1L << nbits;
+		    nbits < 8*sizeof(long)) imm |= -1UL << nbits;
 		break;
 	  }
 

vvp/vthread.cc

@@ -3935,9 +3935,9 @@ bool of_MOD_S(vthread_t thr, vvp_code_t)
 	      /* Sign extend the signed operands when needed. */
 	    if (wid < 8*sizeof(long long)) {
 		  if (lv & (1LL << (wid-1)))
-			lv |= -1LL << wid;
+			lv |= -1ULL << wid;
 		  if (rv & (1LL << (wid-1)))
-			rv |= -1LL << wid;
+			rv |= -1ULL << wid;
 	    }
 
 	    lv %= rv;
@@ -4089,7 +4089,7 @@ static bool of_PARTI_base(vthread_t thr, vvp_code_t cp, bool signed_flag)
 	// NOTE: This is treating the vector as signed. Is that correct?
       int32_t use_base = base;
       if (signed_flag && bwid < 32 && (base&(1<<(bwid-1)))) {
-	    use_base |= (-1) << bwid;
+	    use_base |= -1UL << bwid;
       }
 
       if (use_base >= (int32_t)value.size()) {

vvp/vvp_net.cc

@@ -987,8 +987,8 @@ void vvp_vector4_t::resize(unsigned newsize, vvp_bit4_t pad_bit)
 		    // no need for re-allocation so we are done now.
 		  if (newsize > size_) {
 			if (unsigned fill = size_ % BITS_PER_WORD) {
-			      abits_ptr_[cnt-1] &= ~((-1L) << fill);
-			      bbits_ptr_[cnt-1] &= ~((-1L) << fill);
+			      abits_ptr_[cnt-1] &= ~((-1UL) << fill);
+			      bbits_ptr_[cnt-1] &= ~((-1UL) << fill);
 			      abits_ptr_[cnt-1] |= word_pad_abits << fill;
 			      bbits_ptr_[cnt-1] |= word_pad_bbits << fill;
 			}
@@ -1018,9 +1018,9 @@ void vvp_vector4_t::resize(unsigned newsize, vvp_bit4_t pad_bit)
 
 	    if (newsize > size_) {
 		  if (unsigned fill = size_ % BITS_PER_WORD) {
-			newbits[cnt-1] &= ~((-1L) << fill);
+			newbits[cnt-1] &= ~((-1UL) << fill);
 			newbits[cnt-1] |= word_pad_abits << fill;
-			newbits[newcnt+cnt-1] &= ~((-1L) << fill);
+			newbits[newcnt+cnt-1] &= ~((-1UL) << fill);
 			newbits[newcnt+cnt-1] |= word_pad_bbits << fill;
 		  }
 		  for (unsigned idx = cnt ;  idx < newcnt ;  idx += 1)
@@ -1043,8 +1043,8 @@ void vvp_vector4_t::resize(unsigned newsize, vvp_bit4_t pad_bit)
 	    }
 
 	    if (newsize > size_) {
-		  abits_val_ &= ~((-1L) << size_);
-		  bbits_val_ &= ~((-1L) << size_);
+		  abits_val_ &= ~((-1UL) << size_);
+		  bbits_val_ &= ~((-1UL) << size_);
 		  abits_val_ |= word_pad_abits << size_;
 		  bbits_val_ |= word_pad_bbits << size_;
 	    }
@@ -2018,7 +2018,7 @@ template <class INT>bool vector4_to_value(const vvp_vector4_t&vec, INT&val,
 
       if (is_signed && vec.value(vec.size()-1) == BIT4_1) {
 	    if (vec.size() < 8*sizeof(val))
-		  res |= (~static_cast<INT>(0)) << vec.size();
+		  res |= static_cast<INT>(-1ULL << vec.size());
       }
 
       val = res;