add note to disabled tests, improve comptime cmpxchg

Author: Vexu

lib/std/atomic/stack.zig

@@ -38,8 +38,8 @@ pub fn Stack(comptime T: type) type {
                 node.next = self.root;
                 self.root = node;
             } else {
-                while (@atomicRmw(bool, &self.lock, .Xchg, true, .SeqCst) != false) {}
-                defer assert(@atomicRmw(bool, &self.lock, .Xchg, false, .SeqCst) == true);
+                while (@atomicRmw(bool, &self.lock, .Xchg, true, .SeqCst)) {}
+                defer assert(@atomicRmw(bool, &self.lock, .Xchg, false, .SeqCst));
 
                 node.next = self.root;
                 self.root = node;
@@ -52,8 +52,8 @@ pub fn Stack(comptime T: type) type {
                 self.root = root.next;
                 return root;
             } else {
-                while (@atomicRmw(bool, &self.lock, .Xchg, true, .SeqCst) != false) {}
-                defer assert(@atomicRmw(bool, &self.lock, .Xchg, false, .SeqCst) == true);
+                while (@atomicRmw(bool, &self.lock, .Xchg, true, .SeqCst)) {}
+                defer assert(@atomicRmw(bool, &self.lock, .Xchg, false, .SeqCst));
 
                 const root = self.root orelse return null;
                 self.root = root.next;
@@ -164,7 +164,7 @@ fn startPuts(ctx: *Context) u8 {
 
 fn startGets(ctx: *Context) u8 {
     while (true) {
-        const last = @atomicLoad(bool, &ctx.puts_done, .SeqCst) == true;
+        const last = @atomicLoad(bool, &ctx.puts_done, .SeqCst);
 
         while (ctx.stack.pop()) |node| {
             std.time.sleep(1); // let the os scheduler be our fuzz

lib/std/event/channel.zig

@@ -169,8 +169,7 @@ pub fn Channel(comptime T: type) type {
 
             lock: while (true) {
                 // set the lock flag
-                const prev_lock = @atomicRmw(bool, &self.dispatch_lock, .Xchg, true, .SeqCst);
-                if (prev_lock != 0) return;
+                if (@atomicRmw(bool, &self.dispatch_lock, .Xchg, true, .SeqCst)) return;
 
                 // clear the need_dispatch flag since we're about to do it
                 @atomicStore(bool, &self.need_dispatch, false, .SeqCst);
@@ -250,11 +249,9 @@ pub fn Channel(comptime T: type) type {
                     }
 
                     // clear need-dispatch flag
-                    const need_dispatch = @atomicRmw(bool, &self.need_dispatch, .Xchg, false, .SeqCst);
-                    if (need_dispatch) continue;
+                    if (@atomicRmw(bool, &self.need_dispatch, .Xchg, false, .SeqCst)) continue;
 
-                    const my_lock = @atomicRmw(bool, &self.dispatch_lock, .Xchg, false, .SeqCst);
-                    assert(my_lock);
+                    assert(@atomicRmw(bool, &self.dispatch_lock, .Xchg, false, .SeqCst));
 
                     // we have to check again now that we unlocked
                     if (@atomicLoad(bool, &self.need_dispatch, .SeqCst)) continue :lock;

src/ir.cpp

@@ -25215,21 +25215,25 @@ static IrInstGen *ir_analyze_instruction_cmpxchg(IrAnalyze *ira, IrInstSrcCmpxch
         if (ptr_val == nullptr)
             return ira->codegen->invalid_inst_gen;
 
-        ZigValue *op1_val = const_ptr_pointee(ira, ira->codegen, ptr_val, instruction->base.base.source_node);
-        if (op1_val == nullptr)
+        ZigValue *stored_val = const_ptr_pointee(ira, ira->codegen, ptr_val, instruction->base.base.source_node);
+        if (stored_val == nullptr)
             return ira->codegen->invalid_inst_gen;
 
-        ZigValue *op2_val = ir_resolve_const(ira, casted_cmp_value, UndefBad);
-        if (op2_val == nullptr)
+        ZigValue *expected_val = ir_resolve_const(ira, casted_cmp_value, UndefBad);
+        if (expected_val == nullptr)
+            return ira->codegen->invalid_inst_gen;
+
+        ZigValue *new_val = ir_resolve_const(ira, casted_new_value, UndefBad);
+        if (new_val == nullptr)
             return ira->codegen->invalid_inst_gen;
 
-        bool eql = const_values_equal(ira->codegen, op1_val, op2_val);
+        bool eql = const_values_equal(ira->codegen, stored_val, expected_val);
         IrInstGen *result = ir_const(ira, &instruction->base.base, result_type);
         if (eql) {
-            ir_analyze_store_ptr(ira, &instruction->base.base, casted_ptr, casted_new_value, false);
+            copy_const_val(ira->codegen, stored_val, new_val);
             set_optional_value_to_null(result->value);
         } else {
-            set_optional_payload(result->value, op1_val);
+            set_optional_payload(result->value, stored_val);
         }
         return result;
     }

test/stage1/behavior/atomics.zig

@@ -149,6 +149,7 @@ fn testAtomicStore() void {
 }
 
 test "atomicrmw with floats" {
+    // TODO https://github.com/ziglang/zig/issues/4457
     if (builtin.arch == .aarch64 or builtin.arch == .arm or builtin.arch == .riscv64)
         return error.SkipZigTest;
     testAtomicRmwFloat();
@@ -167,8 +168,6 @@ fn testAtomicRmwFloat() void {
 }
 
 test "atomicrmw with ints" {
-    if (builtin.arch == .mipsel)
-        return error.SkipZigTest;
     testAtomicRmwInt();
     comptime testAtomicRmwInt();
 }
@@ -189,6 +188,9 @@ fn testAtomicRmwInt() void {
     expect(x == 0xff);
     _ = @atomicRmw(u8, &x, .Xor, 2, .SeqCst);
     expect(x == 0xfd);
+
+    // TODO https://github.com/ziglang/zig/issues/4724
+    if (builtin.arch == .mipsel) return;
     _ = @atomicRmw(u8, &x, .Max, 1, .SeqCst);
     expect(x == 0xfd);
     _ = @atomicRmw(u8, &x, .Min, 1, .SeqCst);