disable failing arm-linux non-llvm backend tests

See #13623

Author: andrewrk

src/test.zig

@@ -1816,7 +1816,13 @@ pub const TestContext = struct {
                                 try argv.appendSlice(&.{ "-I", p });
                             }
                         } else switch (host.getExternalExecutor(target_info, .{ .link_libc = case.link_libc })) {
-                            .native => try argv.append(exe_path),
+                            .native => {
+                                if (case.backend == .stage2 and case.target.getCpuArch() == .arm) {
+                                    // https://github.com/ziglang/zig/issues/13623
+                                    continue :update; // Pass test.
+                                }
+                                try argv.append(exe_path);
+                            },
                             .bad_dl, .bad_os_or_cpu => continue :update, // Pass test.
 
                             .rosetta => if (enable_rosetta) {

test/tests.zig

@@ -81,20 +81,22 @@ const test_targets = blk: {
             .single_threaded = true,
             .backend = .stage2_wasm,
         },
-        .{
-            .target = .{
-                .cpu_arch = .arm,
-                .os_tag = .linux,
-            },
-            .backend = .stage2_arm,
-        },
-        .{
-            .target = CrossTarget.parse(.{
-                .arch_os_abi = "arm-linux-none",
-                .cpu_features = "generic+v8a",
-            }) catch unreachable,
-            .backend = .stage2_arm,
-        },
+        // https://github.com/ziglang/zig/issues/13623
+        //.{
+        //    .target = .{
+        //        .cpu_arch = .arm,
+        //        .os_tag = .linux,
+        //    },
+        //    .backend = .stage2_arm,
+        //},
+        // https://github.com/ziglang/zig/issues/13623
+        //.{
+        //    .target = CrossTarget.parse(.{
+        //        .arch_os_abi = "arm-linux-none",
+        //        .cpu_features = "generic+v8a",
+        //    }) catch unreachable,
+        //    .backend = .stage2_arm,
+        //},
         .{
             .target = .{
                 .cpu_arch = .aarch64,