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andrewrkandrewrk
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Merge pull request #7165 from LemonBoy/ppc64final
Make the PPC64 port usable
2 parents 8cf319d + 2193bbf commit bf0cc32

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5 files changed

+81
-49
lines changed

5 files changed

+81
-49
lines changed

‎lib/std/os/linux.zig

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1098,6 +1098,8 @@ pub fn lstat(pathname: [*:0]const u8, statbuf: *kernel_stat) usize {
10981098
pub fn fstatat(dirfd: i32, path: [*:0]const u8, stat_buf: *kernel_stat, flags: u32) usize {
10991099
if (@hasField(SYS, "fstatat64")) {
11001100
return syscall4(.fstatat64, @bitCast(usize, @as(isize, dirfd)), @ptrToInt(path), @ptrToInt(stat_buf), flags);
1101+
} else if (@hasField(SYS, "newfstatat")) {
1102+
return syscall4(.newfstatat, @bitCast(usize, @as(isize, dirfd)), @ptrToInt(path), @ptrToInt(stat_buf), flags);
11011103
} else {
11021104
return syscall4(.fstatat, @bitCast(usize, @as(isize, dirfd)), @ptrToInt(path), @ptrToInt(stat_buf), flags);
11031105
}

‎lib/std/special/c.zig

Lines changed: 49 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -386,6 +386,11 @@ fn clone() callconv(.Naked) void {
386386
);
387387
},
388388
.arm => {
389+
// __clone(func, stack, flags, arg, ptid, tls, ctid)
390+
// r0, r1, r2, r3, +0, +4, +8
391+
392+
// syscall(SYS_clone, flags, stack, ptid, tls, ctid)
393+
// r7 r0, r1, r2, r3, r4
389394
asm volatile (
390395
\\ stmfd sp!,{r4,r5,r6,r7}
391396
\\ mov r7,#120
@@ -445,6 +450,11 @@ fn clone() callconv(.Naked) void {
445450
);
446451
},
447452
.mips, .mipsel => {
453+
// __clone(func, stack, flags, arg, ptid, tls, ctid)
454+
// 3, 4, 5, 6, 7, 8, 9
455+
456+
// syscall(SYS_clone, flags, stack, ptid, tls, ctid)
457+
// 2 4, 5, 6, 7, 8
448458
asm volatile (
449459
\\ # Save function pointer and argument pointer on new thread stack
450460
\\ and $5, $5, -8
@@ -465,12 +475,14 @@ fn clone() callconv(.Naked) void {
465475
\\ addu $sp, $sp, 16
466476
\\ jr $ra
467477
\\ subu $2, $0, $2
468-
\\1: beq $2, $0, 1f
478+
\\1:
479+
\\ beq $2, $0, 1f
469480
\\ nop
470481
\\ addu $sp, $sp, 16
471482
\\ jr $ra
472483
\\ nop
473-
\\1: lw $25, 0($sp)
484+
\\1:
485+
\\ lw $25, 0($sp)
474486
\\ lw $4, 4($sp)
475487
\\ jalr $25
476488
\\ nop
@@ -480,51 +492,48 @@ fn clone() callconv(.Naked) void {
480492
);
481493
},
482494
.powerpc64, .powerpc64le => {
495+
// __clone(func, stack, flags, arg, ptid, tls, ctid)
496+
// 3, 4, 5, 6, 7, 8, 9
497+
498+
// syscall(SYS_clone, flags, stack, ptid, tls, ctid)
499+
// 0 3, 4, 5, 6, 7
483500
asm volatile (
484-
\\ # store non-volatile regs r30, r31 on stack in order to put our
485-
\\ # start func and its arg there
486-
\\ stwu 30, -16(1)
487-
\\ stw 31, 4(1)
488-
\\ # save r3 (func) into r30, and r6(arg) into r31
489-
\\ mr 30, 3
490-
\\ mr 31, 6
491501
\\ # create initial stack frame for new thread
492-
\\ clrrwi 4, 4, 4
493-
\\ li 0, 0
494-
\\ stwu 0, -16(4)
495-
\\ #move c into first arg
496-
\\ mr 3, 5
497-
\\ mr 5, 7
498-
\\ mr 6, 8
499-
\\ mr 7, 9
500-
\\ # move syscall number into r0
501-
\\ li 0, 120
502+
\\ clrrdi 4, 4, 4
503+
\\ li 0, 0
504+
\\ stdu 0,-32(4)
505+
\\
506+
\\ # save fn and arg to child stack
507+
\\ std 3, 8(4)
508+
\\ std 6, 16(4)
509+
\\
510+
\\ # shuffle args into correct registers and call SYS_clone
511+
\\ mr 3, 5
512+
\\ #mr 4, 4
513+
\\ mr 5, 7
514+
\\ mr 6, 8
515+
\\ mr 7, 9
516+
\\ li 0, 120 # SYS_clone = 120
502517
\\ sc
503-
\\ # check for syscall error
504-
\\ bns+ 1f # jump to label 1 if no summary overflow.
505-
\\ #else
506-
\\ neg 3, 3 #negate the result (errno)
518+
\\
519+
\\ # if error, negate return (errno)
520+
\\ bns+ 1f
521+
\\ neg 3, 3
522+
\\
507523
\\1:
508-
\\ # compare sc result with 0
524+
\\ # if we're the parent, return
509525
\\ cmpwi cr7, 3, 0
510-
\\ # if not 0, jump to end
511-
\\ bne cr7, 2f
512-
\\ #else: we're the child
513-
\\ #call funcptr: move arg (d) into r3
514-
\\ mr 3, 31
515-
\\ #move r30 (funcptr) into CTR reg
516-
\\ mtctr 30
517-
\\ # call CTR reg
526+
\\ bnelr cr7
527+
\\
528+
\\ # we're the child. call fn(arg)
529+
\\ ld 3, 16(1)
530+
\\ ld 12, 8(1)
531+
\\ mtctr 12
518532
\\ bctrl
519-
\\ # mov SYS_exit into r0 (the exit param is already in r3)
520-
\\ li 0, 1
533+
\\
534+
\\ # call SYS_exit. exit code is already in r3 from fn return value
535+
\\ li 0, 1 # SYS_exit = 1
521536
\\ sc
522-
\\2:
523-
\\ # restore stack
524-
\\ lwz 30, 0(1)
525-
\\ lwz 31, 4(1)
526-
\\ addi 1, 1, 16
527-
\\ blr
528537
);
529538
},
530539
.sparcv9 => {

‎lib/std/target.zig

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1123,7 +1123,9 @@ pub const Target = struct {
11231123
.mips, .mipsel => &mips.cpu.mips32,
11241124
.mips64, .mips64el => &mips.cpu.mips64,
11251125
.msp430 => &msp430.cpu.generic,
1126-
.powerpc, .powerpc64, .powerpc64le => &powerpc.cpu.generic,
1126+
.powerpc => &powerpc.cpu.ppc32,
1127+
.powerpc64 => &powerpc.cpu.ppc64,
1128+
.powerpc64le => &powerpc.cpu.ppc64le,
11271129
.amdgcn => &amdgpu.cpu.generic,
11281130
.riscv32 => &riscv.cpu.generic_rv32,
11291131
.riscv64 => &riscv.cpu.generic_rv64,

‎test/stage1/behavior/vector.zig

Lines changed: 26 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -149,15 +149,33 @@ test "vector casts of sizes not divisable by 8" {
149149

150150
test "vector @splat" {
151151
const S = struct {
152+
fn testForT(comptime N: comptime_int, v: anytype) void {
153+
const T = @TypeOf(v);
154+
var vec = @splat(N, v);
155+
expectEqual(Vector(N, T), @TypeOf(vec));
156+
var as_array = @as([N]T, vec);
157+
for (as_array) |elem| expectEqual(v, elem);
158+
}
152159
fn doTheTest() void {
153-
var v: u32 = 5;
154-
var x = @splat(4, v);
155-
expect(@TypeOf(x) == Vector(4, u32));
156-
var array_x: [4]u32 = x;
157-
expect(array_x[0] == 5);
158-
expect(array_x[1] == 5);
159-
expect(array_x[2] == 5);
160-
expect(array_x[3] == 5);
160+
// Splats with multiple-of-8 bit types that fill a 128bit vector.
161+
testForT(16, @as(u8, 0xEE));
162+
testForT(8, @as(u16, 0xBEEF));
163+
testForT(4, @as(u32, 0xDEADBEEF));
164+
testForT(2, @as(u64, 0xCAFEF00DDEADBEEF));
165+
166+
testForT(8, @as(f16, 3.1415));
167+
testForT(4, @as(f32, 3.1415));
168+
testForT(2, @as(f64, 3.1415));
169+
170+
// Same but fill more than 128 bits.
171+
testForT(16 * 2, @as(u8, 0xEE));
172+
testForT(8 * 2, @as(u16, 0xBEEF));
173+
testForT(4 * 2, @as(u32, 0xDEADBEEF));
174+
testForT(2 * 2, @as(u64, 0xCAFEF00DDEADBEEF));
175+
176+
testForT(8 * 2, @as(f16, 3.1415));
177+
testForT(4 * 2, @as(f32, 3.1415));
178+
testForT(2 * 2, @as(f64, 3.1415));
161179
}
162180
};
163181
S.doTheTest();

‎test/stage1/behavior/widening.zig

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,7 @@ test "float widening" {
3131
test "float widening f16 to f128" {
3232
// TODO https://github.com/ziglang/zig/issues/3282
3333
if (@import("builtin").arch == .aarch64) return error.SkipZigTest;
34+
if (@import("builtin").arch == .powerpc64le) return error.SkipZigTest;
3435

3536
var x: f16 = 12.34;
3637
var y: f128 = x;

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