diff --git a/lib/std/Target.zig b/lib/std/Target.zig
index dc5da4a8ae5a..4cbeca52eb9f 100644
--- a/lib/std/Target.zig
+++ b/lib/std/Target.zig
@@ -1891,12 +1891,12 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {
         .sparc,
         .spirv32,
         .loongarch32,
+        .dxil,
         .xtensa,
         => 32,
 
         .aarch64,
         .aarch64_be,
-        .dxil,
         .mips64,
         .mips64el,
         .powerpc64,
@@ -2295,15 +2295,18 @@ pub fn c_type_bit_size(target: Target, c_type: CType) u16 {
             .short, .ushort => return 16,
             .int, .uint, .float => return 32,
             .long, .ulong, .longlong, .ulonglong, .double => return 64,
-            .longdouble => return 64,
+            .longdouble => return 128,
         },
 
         .opencl, .vulkan => switch (c_type) {
             .char => return 8,
             .short, .ushort => return 16,
             .int, .uint, .float => return 32,
-            .long, .ulong, .longlong, .ulonglong, .double => return 64,
-            .longdouble => return 64,
+            .long, .ulong, .double => return 64,
+            .longlong, .ulonglong => return 128,
+            // Note: The OpenCL specification does not guarantee a particular size for long double,
+            // but clang uses 128 bits.
+            .longdouble => return 128,
         },
 
         .ps4, .ps5 => switch (c_type) {
@@ -2378,6 +2381,7 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {
             .csky,
             .x86,
             .xcore,
+            .dxil,
             .loongarch32,
             .kalimba,
             .spu_2,
@@ -2387,7 +2391,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {
             .amdgcn,
             .bpfel,
             .bpfeb,
-            .dxil,
             .hexagon,
             .m68k,
             .mips,
@@ -2397,9 +2400,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {
             .nvptx,
             .nvptx64,
             .s390x,
-            .spirv,
-            .spirv32,
-            .spirv64,
             => 8,
 
             .aarch64,
@@ -2414,6 +2414,9 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {
             .riscv32,
             .riscv64,
             .sparc64,
+            .spirv,
+            .spirv32,
+            .spirv64,
             .x86_64,
             .ve,
             .wasm32,
@@ -2482,6 +2485,7 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {
 
             .csky,
             .xcore,
+            .dxil,
             .loongarch32,
             .kalimba,
             .spu_2,
@@ -2497,7 +2501,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {
             .amdgcn,
             .bpfel,
             .bpfeb,
-            .dxil,
             .hexagon,
             .x86,
             .m68k,
@@ -2508,9 +2511,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {
             .nvptx,
             .nvptx64,
             .s390x,
-            .spirv,
-            .spirv32,
-            .spirv64,
             => 8,
 
             .aarch64,
@@ -2525,6 +2525,9 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {
             .riscv32,
             .riscv64,
             .sparc64,
+            .spirv,
+            .spirv32,
+            .spirv64,
             .x86_64,
             .ve,
             .wasm32,
diff --git a/src/codegen/llvm.zig b/src/codegen/llvm.zig
index 1ba1ed8b6fe6..62bcc9ff2410 100644
--- a/src/codegen/llvm.zig
+++ b/src/codegen/llvm.zig
@@ -89,7 +89,14 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
         .spu_2 => return error.@"LLVM backend does not support SPU Mark II",
     };
     try llvm_triple.appendSlice(llvm_arch);
-    try llvm_triple.appendSlice("-unknown-");
+
+    // Unlike CPU backends, GPU backends actually care about the vendor tag.
+    try llvm_triple.appendSlice(switch (target.cpu.arch) {
+        .amdgcn => if (target.os.tag == .mesa3d) "-mesa-" else "-amd-",
+        .nvptx, .nvptx64 => "-nvidia-",
+        .spirv64 => if (target.os.tag == .amdhsa) "-amd-" else "-unknown-",
+        else => "-unknown-",
+    });
 
     const llvm_os = switch (target.os.tag) {
         .freestanding => "unknown",
@@ -109,6 +116,7 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
         .cuda => "cuda",
         .nvcl => "nvcl",
         .amdhsa => "amdhsa",
+        .opencl => "unknown", // https://llvm.org/docs/SPIRVUsage.html#target-triples
         .ps4 => "ps4",
         .ps5 => "ps5",
         .elfiamcu => "elfiamcu",
@@ -130,7 +138,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
         .serenity => "serenity",
         .vulkan => "vulkan",
 
-        .opencl,
         .glsl450,
         .plan9,
         .minix,