From c11b997662c97725f88f5ce5c73ce76dbc199140 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= Date: Wed, 7 Aug 2024 21:26:59 +0200 Subject: [PATCH 1/8] llvm: Set vendor tag in target triple for GPU backends. --- src/codegen/llvm.zig | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/codegen/llvm.zig b/src/codegen/llvm.zig index 1ba1ed8b6fe6..5258e343e024 100644 --- a/src/codegen/llvm.zig +++ b/src/codegen/llvm.zig @@ -89,7 +89,14 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 { .spu_2 => return error.@"LLVM backend does not support SPU Mark II", }; try llvm_triple.appendSlice(llvm_arch); - try llvm_triple.appendSlice("-unknown-"); + + // Unlike CPU backends, GPU backends actually care about the vendor tag. + try llvm_triple.appendSlice(switch (target.cpu.arch) { + .amdgcn => if (target.os.tag == .mesa3d) "-mesa-" else "-amd-", + .nvptx, .nvptx64 => "-nvidia-", + .spirv64 => if (target.os.tag == .amdhsa) "-amd-" else "-unknown-", + else => "-unknown-", + }); const llvm_os = switch (target.os.tag) { .freestanding => "unknown", From 4e566536287d8e2fbc6e01a5bb865c41ac2c4956 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= Date: Wed, 7 Aug 2024 21:41:59 +0200 Subject: [PATCH 2/8] llvm: Add a comment clarifying our mapping of the opencl OS tag. --- src/codegen/llvm.zig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/codegen/llvm.zig b/src/codegen/llvm.zig index 5258e343e024..62bcc9ff2410 100644 --- a/src/codegen/llvm.zig +++ b/src/codegen/llvm.zig @@ -116,6 +116,7 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 { .cuda => "cuda", .nvcl => "nvcl", .amdhsa => "amdhsa", + .opencl => "unknown", // https://llvm.org/docs/SPIRVUsage.html#target-triples .ps4 => "ps4", .ps5 => "ps5", .elfiamcu => "elfiamcu", @@ -137,7 +138,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 { .serenity => "serenity", .vulkan => "vulkan", - .opencl, .glsl450, .plan9, .minix, From 1e1cd1f02c98bd63bbeb308f827922f4f3fa1a84 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= Date: Thu, 8 Aug 2024 02:02:11 +0200 Subject: [PATCH 3/8] Revert "std.Target: Fix C long double size for amdhsa, amdpal, and mesa3d (8, not 16)." This reverts commit eef499812c37112f4b03bde73a632c23ca753d20. --- lib/std/Target.zig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/std/Target.zig b/lib/std/Target.zig index dc5da4a8ae5a..4a0ef367189d 100644 --- a/lib/std/Target.zig +++ b/lib/std/Target.zig @@ -2295,7 +2295,7 @@ pub fn c_type_bit_size(target: Target, c_type: CType) u16 { .short, .ushort => return 16, .int, .uint, .float => return 32, .long, .ulong, .longlong, .ulonglong, .double => return 64, - .longdouble => return 64, + .longdouble => return 128, }, .opencl, .vulkan => switch (c_type) { From 93e983489b437d4997938e540422b09aaadbebed Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= Date: Thu, 8 Aug 2024 02:02:22 +0200 Subject: [PATCH 4/8] Revert "std.Target: Fix C long double size for opencl (8, not 16)." This reverts commit a1d3e567635e79e0fbd8d56225d5098bc6cb8bbb. --- lib/std/Target.zig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/lib/std/Target.zig b/lib/std/Target.zig index 4a0ef367189d..64608181fc8e 100644 --- a/lib/std/Target.zig +++ b/lib/std/Target.zig @@ -2303,7 +2303,9 @@ pub fn c_type_bit_size(target: Target, c_type: CType) u16 { .short, .ushort => return 16, .int, .uint, .float => return 32, .long, .ulong, .longlong, .ulonglong, .double => return 64, - .longdouble => return 64, + // Note: The OpenCL specification does not guarantee a particular size for long double, + // but clang uses 128 bits. + .longdouble => return 128, }, .ps4, .ps5 => switch (c_type) { From ecf2069e305c55d0b9482a795ddaa710999fedc2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= Date: Thu, 8 Aug 2024 02:02:33 +0200 Subject: [PATCH 5/8] Revert "std.Target: Fix C long long size for opencl (8, not 16)." This reverts commit 606d011acf8c2a75ea1485174c2c1d24a612c86b. --- lib/std/Target.zig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/lib/std/Target.zig b/lib/std/Target.zig index 64608181fc8e..410bcbd1e2d5 100644 --- a/lib/std/Target.zig +++ b/lib/std/Target.zig @@ -2302,7 +2302,8 @@ pub fn c_type_bit_size(target: Target, c_type: CType) u16 { .char => return 8, .short, .ushort => return 16, .int, .uint, .float => return 32, - .long, .ulong, .longlong, .ulonglong, .double => return 64, + .long, .ulong, .double => return 64, + .longlong, .ulonglong => return 128, // Note: The OpenCL specification does not guarantee a particular size for long double, // but clang uses 128 bits. .longdouble => return 128, From d415efd68f8e87e6ac5edd9b67c518de106fed55 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= Date: Thu, 8 Aug 2024 02:02:50 +0200 Subject: [PATCH 6/8] Revert "std.Target: Fix C type alignment calculation for dxil." This reverts commit e67388c2e538789aa3e46f625f6e08696093dcdb. --- lib/std/Target.zig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/std/Target.zig b/lib/std/Target.zig index 410bcbd1e2d5..46c22e2daf05 100644 --- a/lib/std/Target.zig +++ b/lib/std/Target.zig @@ -2381,6 +2381,7 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 { .csky, .x86, .xcore, + .dxil, .loongarch32, .kalimba, .spu_2, @@ -2390,7 +2391,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 { .amdgcn, .bpfel, .bpfeb, - .dxil, .hexagon, .m68k, .mips, @@ -2485,6 +2485,7 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 { .csky, .xcore, + .dxil, .loongarch32, .kalimba, .spu_2, @@ -2500,7 +2501,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 { .amdgcn, .bpfel, .bpfeb, - .dxil, .hexagon, .x86, .m68k, From 1b6b8813cf95e2ad5170ffb1e80531c635679cc6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= Date: Thu, 8 Aug 2024 02:03:17 +0200 Subject: [PATCH 7/8] Revert "std.Target: Fix ptrBitWidth_cpu_abi() for dxil (64-bit, not 32-bit)." This reverts commit ab154be7f0a89b271686d740f7e50545414a6024. --- lib/std/Target.zig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/std/Target.zig b/lib/std/Target.zig index 46c22e2daf05..b6b20c373318 100644 --- a/lib/std/Target.zig +++ b/lib/std/Target.zig @@ -1891,12 +1891,12 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 { .sparc, .spirv32, .loongarch32, + .dxil, .xtensa, => 32, .aarch64, .aarch64_be, - .dxil, .mips64, .mips64el, .powerpc64, From bf47cb4379519b3af4610696cf25a7f325866d72 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= Date: Thu, 8 Aug 2024 02:41:17 +0200 Subject: [PATCH 8/8] std.Target: Fix C type alignment calculation for spirv. --- lib/std/Target.zig | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/lib/std/Target.zig b/lib/std/Target.zig index b6b20c373318..4cbeca52eb9f 100644 --- a/lib/std/Target.zig +++ b/lib/std/Target.zig @@ -2400,9 +2400,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 { .nvptx, .nvptx64, .s390x, - .spirv, - .spirv32, - .spirv64, => 8, .aarch64, @@ -2417,6 +2414,9 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 { .riscv32, .riscv64, .sparc64, + .spirv, + .spirv32, + .spirv64, .x86_64, .ve, .wasm32, @@ -2511,9 +2511,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 { .nvptx, .nvptx64, .s390x, - .spirv, - .spirv32, - .spirv64, => 8, .aarch64, @@ -2528,6 +2525,9 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 { .riscv32, .riscv64, .sparc64, + .spirv, + .spirv32, + .spirv64, .x86_64, .ve, .wasm32,