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tests/tcg/ppc64[le]: test plxssp and pstxssp #68

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db3b2a0
target/ppc: implement plxsd/pstxsd
Jan 10, 2022
e2bafaa
target/ppc: implement plxssp/pstxssp
Jan 19, 2022
35fc421
tests/tcg/ppc64[le]: add test for plxsd and pstxsd
Jan 13, 2022
b76c3df
tests/tcg/ppc64[le]: test plxssp and pstxssp
Jan 19, 2022
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4 changes: 4 additions & 0 deletions target/ppc/insn32.decode
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Original file line number Diff line number Diff line change
Expand Up @@ -540,6 +540,10 @@ VCLRRB 000100 ..... ..... ..... 00111001101 @VX

# VSX Load/Store Instructions

LXSD 111001 ..... ..... .............. 10 @DS
STXSD 111101 ..... ..... .............. 10 @DS
LXSSP 111001 ..... ..... .............. 11 @DS
STXSSP 111101 ..... ..... .............. 11 @DS
LXV 111101 ..... ..... ............ . 001 @DQ_TSX
STXV 111101 ..... ..... ............ . 101 @DQ_TSX
LXVP 000110 ..... ..... ............ 0000 @DQ_TSXP
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16 changes: 16 additions & 0 deletions target/ppc/insn64.decode
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Expand Up @@ -32,6 +32,10 @@
...... ..... ra:5 ................ \
&PLS_D si=%pls_si rt=%rt_tsxp

@8LS_D ...... .. . .. r:1 .. .................. \
...... rt:5 ra:5 ................ \
&PLS_D si=%pls_si

# Format 8RR:D
%8rr_si 32:s16 0:16
%8rr_xt 16:1 21:5
Expand Down Expand Up @@ -180,6 +184,18 @@ PSTFD 000001 10 0--.-- .................. \

### VSX instructions

PLXSD 000001 00 0--.-- .................. \
101010 ..... ..... ................ @8LS_D

PSTXSD 000001 00 0--.-- .................. \
101110 ..... ..... ................ @8LS_D

PLXSSP 000001 00 0--.-- .................. \
101011 ..... ..... ................ @8LS_D

PSTXSSP 000001 00 0--.-- .................. \
101111 ..... ..... ................ @8LS_D

PLXV 000001 00 0--.-- .................. \
11001 ...... ..... ................ @8LS_D_TSX
PSTXV 000001 00 0--.-- .................. \
Expand Down
39 changes: 7 additions & 32 deletions target/ppc/translate.c
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Expand Up @@ -7502,49 +7502,24 @@ static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a)

#include "translate/branch-impl.c.inc"

/* Handles lfdp, lxsd, lxssp */
/* Handles lfdp */
static void gen_dform39(DisasContext *ctx)
{
switch (ctx->opcode & 0x3) {
case 0: /* lfdp */
if ((ctx->opcode & 0x3) == 0) {
if (ctx->insns_flags2 & PPC2_ISA205) {
return gen_lfdp(ctx);
}
break;
case 2: /* lxsd */
if (ctx->insns_flags2 & PPC2_ISA300) {
return gen_lxsd(ctx);
}
break;
case 3: /* lxssp */
if (ctx->insns_flags2 & PPC2_ISA300) {
return gen_lxssp(ctx);
}
break;
}
return gen_invalid(ctx);
}

/* handles stfdp, lxv, stxsd, stxssp lxvx */
/* Handles stfdp */
static void gen_dform3D(DisasContext *ctx)
{
if ((ctx->opcode & 3) != 1) { /* DS-FORM */
switch (ctx->opcode & 0x3) {
case 0: /* stfdp */
if (ctx->insns_flags2 & PPC2_ISA205) {
return gen_stfdp(ctx);
}
break;
case 2: /* stxsd */
if (ctx->insns_flags2 & PPC2_ISA300) {
return gen_stxsd(ctx);
}
break;
case 3: /* stxssp */
if (ctx->insns_flags2 & PPC2_ISA300) {
return gen_stxssp(ctx);
}
break;
if ((ctx->opcode & 3) == 0) { /* DS-FORM */
/* stfdp */
if (ctx->insns_flags2 & PPC2_ISA205) {
return gen_stfdp(ctx);
}
}
return gen_invalid(ctx);
Expand Down
148 changes: 100 additions & 48 deletions target/ppc/translate/vsx-impl.c.inc
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Expand Up @@ -288,30 +288,6 @@ VSX_VECTOR_LOAD_STORE_LENGTH(stxvl)
VSX_VECTOR_LOAD_STORE_LENGTH(stxvll)
#endif

#define VSX_LOAD_SCALAR_DS(name, operation) \
static void gen_##name(DisasContext *ctx) \
{ \
TCGv EA; \
TCGv_i64 xth; \
\
if (unlikely(!ctx->altivec_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
xth = tcg_temp_new_i64(); \
gen_set_access_type(ctx, ACCESS_INT); \
EA = tcg_temp_new(); \
gen_addr_imm_index(ctx, EA, 0x03); \
gen_qemu_##operation(ctx, xth, EA); \
set_cpu_vsr(rD(ctx->opcode) + 32, xth, true); \
/* NOTE: cpu_vsrl is undefined */ \
tcg_temp_free(EA); \
tcg_temp_free_i64(xth); \
}

VSX_LOAD_SCALAR_DS(lxsd, ld64_i64)
VSX_LOAD_SCALAR_DS(lxssp, ld32fs)

#define VSX_STORE_SCALAR(name, operation) \
static void gen_##name(DisasContext *ctx) \
{ \
Expand Down Expand Up @@ -461,30 +437,6 @@ static void gen_stxvb16x(DisasContext *ctx)
tcg_temp_free_i64(xsl);
}

#define VSX_STORE_SCALAR_DS(name, operation) \
static void gen_##name(DisasContext *ctx) \
{ \
TCGv EA; \
TCGv_i64 xth; \
\
if (unlikely(!ctx->altivec_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
xth = tcg_temp_new_i64(); \
get_cpu_vsr(xth, rD(ctx->opcode) + 32, true); \
gen_set_access_type(ctx, ACCESS_INT); \
EA = tcg_temp_new(); \
gen_addr_imm_index(ctx, EA, 0x03); \
gen_qemu_##operation(ctx, xth, EA); \
/* NOTE: cpu_vsrl is undefined */ \
tcg_temp_free(EA); \
tcg_temp_free_i64(xth); \
}

VSX_STORE_SCALAR_DS(stxsd, st64_i64)
VSX_STORE_SCALAR_DS(stxssp, st32fs)

static void gen_mfvsrwz(DisasContext *ctx)
{
if (xS(ctx->opcode) < 32) {
Expand Down Expand Up @@ -2270,6 +2222,102 @@ static bool do_lstxv_X(DisasContext *ctx, arg_X *a, bool store, bool paired)
return do_lstxv(ctx, a->ra, cpu_gpr[a->rb], a->rt, store, paired);
}

static bool do_lstxsd(DisasContext *ctx, int rt, int ra, TCGv displ, bool store)
{
TCGv ea;
TCGv_i64 xt;
MemOp mop;

if (store) {
REQUIRE_VECTOR(ctx);
} else {
REQUIRE_VSX(ctx);
}

xt = tcg_temp_new_i64();
mop = DEF_MEMOP(MO_UQ);

gen_set_access_type(ctx, ACCESS_INT);
ea = do_ea_calc(ctx, ra, displ);

if (store) {
get_cpu_vsr(xt, rt + 32, true);
tcg_gen_qemu_st_i64(xt, ea, ctx->mem_idx, mop);
} else {
tcg_gen_qemu_ld_i64(xt, ea, ctx->mem_idx, mop);
set_cpu_vsr(rt + 32, xt, true);
set_cpu_vsr(rt + 32, tcg_constant_i64(0), false);
}

tcg_temp_free(ea);
tcg_temp_free_i64(xt);

return true;
}

static bool do_lstxsd_DS(DisasContext *ctx, arg_D *a, bool store)
{
return do_lstxsd(ctx, a->rt, a->ra, tcg_constant_tl(a->si), store);
}

static bool do_plstxsd_PLS_D(DisasContext *ctx, arg_PLS_D *a, bool store)
{
arg_D d;

if (!resolve_PLS_D(ctx, &d, a)) {
return true;
}

return do_lstxsd(ctx, d.rt, d.ra, tcg_constant_tl(d.si), store);
}

static bool do_lstxssp(DisasContext *ctx, int rt, int ra, TCGv displ, bool store)
{
TCGv ea;
TCGv_i64 xt;

REQUIRE_VECTOR(ctx);

xt = tcg_temp_new_i64();

gen_set_access_type(ctx, ACCESS_INT);
ea = do_ea_calc(ctx, ra, displ);

if (store) {
get_cpu_vsr(xt, rt + 32, true);
gen_qemu_st32fs(ctx, xt, ea);
} else {
gen_qemu_ld32fs(ctx, xt, ea);
set_cpu_vsr(rt + 32, xt, true);
set_cpu_vsr(rt + 32, tcg_constant_i64(0), false);
}

tcg_temp_free(ea);
tcg_temp_free_i64(xt);

return true;
}

static bool do_lstxssp_DS(DisasContext *ctx, arg_D *a, bool store)
{
return do_lstxssp(ctx, a->rt, a->ra, tcg_constant_tl(a->si), store);
}

static bool do_plstxssp_PLS_D(DisasContext *ctx, arg_PLS_D *a, bool store)
{
arg_D d;

if (!resolve_PLS_D(ctx, &d, a)) {
return true;
}

return do_lstxssp(ctx, d.rt, d.ra, tcg_constant_tl(d.si), store);
}

TRANS_FLAGS2(ISA300, LXSD, do_lstxsd_DS, false)
TRANS_FLAGS2(ISA300, STXSD, do_lstxsd_DS, true)
TRANS_FLAGS2(ISA300, LXSSP, do_lstxssp_DS, false)
TRANS_FLAGS2(ISA300, STXSSP, do_lstxssp_DS, true)
TRANS_FLAGS2(ISA300, STXV, do_lstxv_D, true, false)
TRANS_FLAGS2(ISA300, LXV, do_lstxv_D, false, false)
TRANS_FLAGS2(ISA310, STXVP, do_lstxv_D, true, true)
Expand All @@ -2278,6 +2326,10 @@ TRANS_FLAGS2(ISA300, STXVX, do_lstxv_X, true, false)
TRANS_FLAGS2(ISA300, LXVX, do_lstxv_X, false, false)
TRANS_FLAGS2(ISA310, STXVPX, do_lstxv_X, true, true)
TRANS_FLAGS2(ISA310, LXVPX, do_lstxv_X, false, true)
TRANS64_FLAGS2(ISA310, PLXSD, do_plstxsd_PLS_D, false)
TRANS64_FLAGS2(ISA310, PSTXSD, do_plstxsd_PLS_D, true)
TRANS64_FLAGS2(ISA310, PLXSSP, do_plstxssp_PLS_D, false)
TRANS64_FLAGS2(ISA310, PSTXSSP, do_plstxssp_PLS_D, true)
TRANS64_FLAGS2(ISA310, PSTXV, do_lstxv_PLS_D, true, false)
TRANS64_FLAGS2(ISA310, PLXV, do_lstxv_PLS_D, false, false)
TRANS64_FLAGS2(ISA310, PSTXVP, do_lstxv_PLS_D, true, true)
Expand Down
10 changes: 10 additions & 0 deletions tests/tcg/ppc64/Makefile.target
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Expand Up @@ -13,6 +13,16 @@ $(PPC64_TESTS): CFLAGS += -mpower8-vector
PPC64_TESTS += byte_reverse
PPC64_TESTS += mtfsf
ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_POWER10),)
PPC64_TESTS += plstxsd plstxssp

plstxsd: CFLAGS += -mpower8-vector
run-plstxsd: QEMU_OPTS+=-cpu POWER10
run-plugin-plstxsd-with-%: QEMU_OPTS+=-cpu POWER10

plstxssp: CFLAGS += -mpower8-vector
run-plstxssp: QEMU_OPTS+=-cpu POWER10
run-plugin-plstxssp-with-%: QEMU_OPTS+=-cpu POWER10

run-byte_reverse: QEMU_OPTS+=-cpu POWER10
run-plugin-byte_reverse-with-%: QEMU_OPTS+=-cpu POWER10
else
Expand Down
10 changes: 9 additions & 1 deletion tests/tcg/ppc64le/Makefile.target
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Expand Up @@ -10,12 +10,20 @@ endif
$(PPC64LE_TESTS): CFLAGS += -mpower8-vector

ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_POWER10),)
PPC64LE_TESTS += byte_reverse
PPC64LE_TESTS += byte_reverse plstxsd plstxssp
endif
byte_reverse: CFLAGS += -mcpu=power10
run-byte_reverse: QEMU_OPTS+=-cpu POWER10
run-plugin-byte_reverse-with-%: QEMU_OPTS+=-cpu POWER10

plstxsd: CFLAGS += -mpower8-vector
run-plstxsd: QEMU_OPTS+=-cpu POWER10
run-plugin-plstxsd-with-%: QEMU_OPTS+=-cpu POWER10

plstxssp: CFLAGS += -mpower8-vector
run-plstxssp: QEMU_OPTS+=-cpu POWER10
run-plugin-plstxssp-with-%: QEMU_OPTS+=-cpu POWER10

PPC64LE_TESTS += mtfsf
PPC64LE_TESTS += signal_save_restore_xer

Expand Down
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