fix(riscv/irqc): align IMSIC handler to AIA specifications #209
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filippofontana
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Had to force push because of the failing format check, I wanted to keep the change small but clang-format doesn't like it 🥲. |
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josecm
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Thanks again for fixing this @filippofontana! |
josecm
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Ok, sure! |
This commit adds a "logical" swap operation to the CSR registers accessors. It is implemented with the `csrrw` instruction under the hood. Signed-off-by: Filippo Fontana <[email protected]>
"The RISC-V Advanced Interrupt Architecture" specifications explain in Chapter 3 (pages 26-27) how interrupts should be handled with IMSIC, in particular, interrupt claiming has to be done right after reading the STOPEI register or in the same read instruction with the csrrw instruction. This commit aligns the IMSIC interrupt handler to that specs. Without this change, if an interrupt with higher priority becomes pending while handling a lower one, writing to STOPEI after `interrupts_handle()` executes will claim the higher IRQ, freezing the execution. Signed-off-by: Filippo Fontana <[email protected]>
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"The RISC-V Advanced Interrupt Architecture" specifications explain in Chapter 3 (pages 26-27) how interrupts should be handled with IMSIC, in particular, interrupt claiming has to be done right after reading the STOPEI register or in the same read instruction with the csrrw instruction.
This commit aligns the IMSIC interrupt handler to that specs. Without this change, if an interrupt with higher priority becomes pending while handling a lower one, writing to STOPEI after
interrupts_handle()executes will claim the higher IRQ, freezing the execution.