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Fix arm pop reg access #2718

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Fix arm pop reg access #2718

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aee0d2f
Sort patches by file name to ensure apply order
jiegec May 24, 2025
7e588f6
Fix register access type in thumb pop instruction
jiegec May 24, 2025
1c64cb1
Add instructions with register list from issue #2710 to tests
jiegec May 24, 2025
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2 changes: 1 addition & 1 deletion arch/ARM/ARMGenCSMappingInsnOp.inc
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Original file line number Diff line number Diff line change
Expand Up @@ -36878,7 +36878,7 @@
{
{ CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
{ CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
{ CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
{ CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
{ CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */
{ 0 }
}},
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13 changes: 13 additions & 0 deletions suite/auto-sync/inc_patches/ARM/04_tPOP_reg_lists_write_attribute.patch
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Original file line number Diff line number Diff line change
@@ -0,0 +1,13 @@
diff --git a/arch/ARM/ARMGenCSMappingInsnOp.inc b/arch/ARM/ARMGenCSMappingInsnOp.inc
index 749cdb85..4abfd4b8 100644
--- a/arch/ARM/ARMGenCSMappingInsnOp.inc
+++ b/arch/ARM/ARMGenCSMappingInsnOp.inc
@@ -36878,7 +36878,7 @@
{
{ CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
{ CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
- { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+ { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
{ CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */
{ 0 }
}},
3 changes: 2 additions & 1 deletion suite/auto-sync/src/autosync/IncGenerator.py
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Original file line number Diff line number Diff line change
Expand Up @@ -140,7 +140,8 @@ def apply_patches(self) -> None:
if not patch_dir.exists():
return

for patch in patch_dir.iterdir():
# apply patches in alphabetical order
for patch in sorted(patch_dir.iterdir()):
try:
subprocess.run(
["git", "apply", "-v", "--recount", str(patch)],
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93 changes: 93 additions & 0 deletions tests/details/arm.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -2825,3 +2825,96 @@ test_cases:
writeback: -1
regs_read: [ r3 ]
regs_write: [ ]
-
input:
bytes: [ 0xf0, 0xbd, 0x03, 0xbc, 0x91, 0xec, 0x08, 0x4a ]
arch: "CS_ARCH_ARM"
options: [ CS_OPT_DETAIL, CS_MODE_THUMB ]
address: 0x0
expected:
insns:
-
asm_text: "pop {r4, r5, r6, r7, pc}"
details:
arm:
operands:
-
type: ARM_OP_REG
reg: r4
access: CS_AC_WRITE
-
type: ARM_OP_REG
reg: r5
access: CS_AC_WRITE
-
type: ARM_OP_REG
reg: r6
access: CS_AC_WRITE
-
type: ARM_OP_REG
reg: r7
access: CS_AC_WRITE
-
type: ARM_OP_REG
reg: r15
access: CS_AC_WRITE
regs_read: [ r13 ]
regs_write: [ r13, r4, r5, r6, r7, r15 ]
-
asm_text: "pop {r0, r1}"
details:
arm:
operands:
-
type: ARM_OP_REG
reg: r0
access: CS_AC_WRITE
-
type: ARM_OP_REG
reg: r1
access: CS_AC_WRITE
regs_read: [ r13 ]
regs_write: [ r13, r0, r1 ]
-
asm_text: "vldmia r1, {s8, s9, s10, s11, s12, s13, s14, s15}"
details:
arm:
operands:
-
type: ARM_OP_REG
reg: r1
access: CS_AC_READ
-
type: ARM_OP_REG
reg: s8
access: CS_AC_WRITE
-
type: ARM_OP_REG
reg: s9
access: CS_AC_WRITE
-
type: ARM_OP_REG
reg: s10
access: CS_AC_WRITE
-
type: ARM_OP_REG
reg: s11
access: CS_AC_WRITE
-
type: ARM_OP_REG
reg: s12
access: CS_AC_WRITE
-
type: ARM_OP_REG
reg: s13
access: CS_AC_WRITE
-
type: ARM_OP_REG
reg: s14
access: CS_AC_WRITE
-
type: ARM_OP_REG
reg: s15
access: CS_AC_WRITE
regs_read: [ r1 ]
regs_write: [ s8, s9, s10, s11, s12, s13, s14, s15 ]
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